IP Library › Granted Patent US 12,585,727
Granted Patent B2
US 12,585,727 · App. 18/754,719 · Granted Mar 24, 2026

Bit matrix multiplication

Inventors: Dmitry Y. Babokin (Santa Clara, CA); Kshitij A. Doshi (Tempe, AZ); Vadim Sukhomlinov (Santa Clara, CA)
Assignee: Intel Corporation
G06F17/16G06F7/5443G06F9/3001G06F9/30029G06F9/30036G06F9/30038
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Quick Facts
Patent No.
US 12,585,727
App. No.
18/754,719
Granted
Mar 24, 2026
Kind
B2
Abstract

Detailed are embodiments related to bit matrix multiplication in a processor. For example, in some embodiments a processor comprising: decode circuitry to decode an instruction have fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate; and execution circuitry to execute the decoded instruction to perform a multiplication of a matrix of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified destination bit matrix, wherein S indicates a plural bit size is described.

Claims (27)

1 . A processor comprising:

decode circuitry to decode an instruction having fields for an opcode, an identifier of a first multi-dimensional source bit matrix, an identifier of a second multi-dimensional source bit matrix, an identifier of a destination multi-dimensional bit matrix, and an operation selector; and

execution circuitry to execute the decoded instruction to perform a bit matrix multiplication and accumulation using the identified first multi-dimensional source bit matrix and the identified second multi-dimensional source bit matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the bit matrix multiplication into the identified destination multi-dimensional bit matrix.

2 . The processor of claim 1 , wherein the operation selector is an immediate.

3 . The processor of claim 2 , wherein bits of the immediate are used to select the accumulation operation of a group of exclusive OR (XOR), AND, OR, and NOR.

4 . The processor of claim 2 , wherein bits of the immediate are used to select the multiplication operation of a group of exclusive OR (XOR), AND, OR, and NOR.

5 . The processor of claim 1 , wherein the identified first multi-dimensional source matrix is an 8×8 bit matrix and the identified second multi-dimensional source bit matrix is an 8×64 bit matrix.

6 . The processor of claim 1 , wherein the identified first multi-dimensional source matrix is a 64×8 bit matrix and the identified second multi-dimensional source bit matrix is an 8×8 bit matrix.

7 . The processor of claim 1 , wherein the identified first multi-dimensional source matrix is an 8×64 bit matrix and the identified second multi-dimensional source bit matrix is a 64×64 bit matrix.

8 . The processor of claim 1 , wherein the identified second multi-dimensional source bit matrix is to be stored in memory.

9 . The processor of claim 1 , wherein the identified first multi-dimensional source matrix is a 64×8 bit matrix and the identified second multi-dimensional source bit matrix is a 64×8 bit matrix.

10 . The processor of claim 1 , wherein the identified first multi-dimensional source bit matrix is to be stored in memory.

11 . The processor of claim 1 , wherein the bit matrix multiplication and accumulation, comprises for each bit position in the destination, to multiply a value from each bit position of a corresponding row in the identified first multi-dimensional source bit matrix by a value of corresponding bit position of a corresponding column in the identified second multi-dimensional source bit matrix, accumulate each of the multiplications, and store a result of the accumulate.

12 . A processor comprising:

decode circuitry to decode an instruction having fields for an opcode, an identifier of a first multi-dimensional source matrix, an identifier of a second multi-dimensional source matrix, an identifier of a multi-dimensional destination matrix, and an operation selector; and

execution circuitry to execute the decoded instruction to perform a multiplication and accumulation using a matrix of S-bit elements of the identified first multi-dimensional source matrix and S-bit elements of the identified second multi-dimensional source matrix, wherein the multiplication and accumulation operations are selected by the operation selector and store a result of the matrix multiplication into the identified multi-dimensional destination matrix, wherein S indicates a plural bit size.

13 . The processor of claim 12 , wherein S indicates a bit size of 1, 2, 4, or 8.

14 . The processor of claim 12 , wherein the operation selector is an immediate.

15 . The processor of claim 14 , wherein bits of the immediate are used to select the accumulation operation of a group of exclusive OR (XOR), AND, OR, and NOR.

16 . The processor of claim 14 , wherein bits of the immediate are used to select the multiplication operation of a group of exclusive OR (XOR), AND, OR, and NOR.

17 . The processor of claim 12 , wherein the identified first multi-dimensional source matrix is an 8×8 bit matrix and the identified second multi-dimensional source matrix is an 8×64 bit matrix.

18 . The processor of claim 12 , wherein the identified first multi-dimensional source matrix is a 64×8 bit matrix and the identified second multi-dimensional source matrix is an 8×8 bit matrix.

19 . The processor of claim 12 , wherein the identified first multi-dimensional source matrix is an 8×64 bit matrix and the identified second multi-dimensional source matrix is a 64×64 bit matrix.

20 . The processor of claim 12 , wherein the identified second multi-dimensional source matrix is stored in memory.

21 . The processor of claim 12 , wherein the identified first multi-dimensional source matrix is a 64×8 bit matrix and the identified second multi-dimensional source bit matrix is a 64×8 bit matrix.

22 . The processor of claim 12 , wherein the identified first multi-dimensional source matrix is stored in memory.

23 . The processor of claim 12 , wherein the matrix multiplication and accumulation, comprises: for each S-bit position group in the destination, to multiply a S-bit group value of each S-bit position group of a corresponding row in the identified first multi-dimensional source matrix by a value of corresponding S-bit position group of a corresponding column in the identified second multi-dimensional source matrix, accumulate each of the multiplications, and store a result of the accumulate.

Continuity (5)
Continuation 18083012 · Dec 16, 2022
Continuation 17156119 · Jan 22, 2021
Continuation 16691327 · Nov 21, 2019
Continuation 15721529 · Sep 29, 2017
Related Publication 20250021621A1 · Jan 16, 2025
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