Method for forming via structure with low resistivity
A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer and first and second gate spacers in first and second openings of the first insulating layer, respectively, forming a first conductive gate stack adjacent to the first gate spacer and forming an insulating material adjacent to the second gate spacer after forming the first conductive gate stack. The method also includes covering the first conductive gate stack and the insulating material with a first insulating capping layer and a second insulating capping layer, respectively, and forming a source/drain contact structure between the first and second gate spacer layers. The top surface of the first insulating layer is higher than those of the insulating material and is substantially level with that of the first conductive gate stack.
1 . A method for forming a semiconductor device structure, comprising:
forming a plurality of gate structures in a first insulating layer, wherein each of the plurality of gate structures comprises a recessed gate electrode layer surrounded by a gate dielectric layer;
removing the recessed gate electrode layer in a first gate structure of the plurality of gate structures to leave a space;
forming an insulating material with a top surface lower than a top surface the gate dielectric layer in the space;
forming insulating capping layers over the recessed gate electrode layer in a second gate structure and a third gate structure of the plurality of gate structures and the insulating material in the space, respectively; and
forming a first source/drain contact structure between the second gate structure and the third gate structure and a second source/drain contact structure between the insulating material and the third gate structure.
2 . The method as claimed in claim 1 , further comprising:
forming a conductive capping layer over the recessed gate electrode layer in the second gate structure and the third gate structure of the plurality of gate structures prior to the removal the recessed gate electrode layer in the first gate structure.
3 . The method as claimed in claim 1 , further comprising:
forming a second insulating over the first insulating layer;
forming first via structure through the second insulating layer and electrically connected to the gate electrode layer;
a second via structure through the second insulating layer and electrically connected to the first source/drain contact structure; and
a third via structure through the second insulating layer and electrically connected to the second source/drain contact structure, wherein the third via structure through covers the insulating capping layer over insulating material.
4 . The method as claimed in claim 3 , wherein the second via structure has a vertical height that is substantially equal to that of the third via structure and lower than that of the first via structure.
5 . The method as claimed in claim 1 , wherein the top surface of the insulating material is higher than a top surface of the recessed gate electrode layer.
6 . A method for forming a semiconductor device structure, comprising:
forming a first recessed gate electrode layer and a second recessed gate electrode layer over and surrounded by a first gate dielectric layer and a second gate dielectric layer, respectively;
removing the first recessed gate electrode layer;
forming an insulating material over and surrounded by the first gate dielectric layer after removing the first recessed gate electrode layer;
recessing the insulating material; and
covering each of a top surface of the recessed insulating material and a top surface of the second recessed gate electrode layer with an insulating capping layer.
7 . The method as claimed in claim 6 , further comprising:
forming a conductive capping layer over the recessed second recessed gate electrode layer prior to coverage of the insulating capping layer.
8 . The method as claimed in claim 7 , further comprising:
removing a portion of the second recessed gate electrode layer prior to formation of the conductive capping layer.
9 . The method as claimed in claim 7 , further comprising:
forming a via structure over and electrically connected to the conductive capping layer.
10 . The method as claimed in claim 6 , further comprising:
forming a first insulating layer over a substrate prior to formation of the first recessed electrode layer and the second recessed gate electrode layer, wherein the first recessed electrode layer and the second recessed gate electrode layer are formed in the first insulating layer.
11 . The method as claimed in claim 10 , further comprising:
forming an opening in the first insulating layer and between the first gate dielectric layer and the second gate dielectric layer; and
forming a source/drain contact structure in the opening, wherein a top surface of the source/drain contact structure is higher than the top surface of the recessed insulating material.
12 . The method as claimed in claim 11 , further comprising:
forming a second insulating layer over the first insulating layer; and
forming a via structure in the second insulating layer and electrically connected to the source/drain contact structure.
13 . The method as claimed in claim 12 , wherein the via structure laterally extends from the top surface of the source/drain contact structure to a top surface of the insulating capping layer.
14 . The method as claimed in claim 11 , wherein formation of the source/drain contact structure comprises:
forming a conductive material in the opening and over a top surface of the insulating capping layer; and
removing a portion of the conductive material over a top surface of the insulating capping layer by polishing.
15 . The method as claimed in claim 6 , wherein the insulating capping layer laterally extended over a top surface of the first gate dielectric layer and a top surface of the second gate dielectric layer.
16 . A method for forming a semiconductor device structure, comprising:
forming a plurality of gate structures over a substrate, wherein each of the plurality of gate structures comprises:
a recessed gate electrode layer;
a conductive capping layer over the recessed gate electrode layer;
a gate dielectric layer surrounding the recessed gate electrode layer and the conductive capping layer; and
a gate spacer separated from the recessed gate electrode layer by the gate dielectric layer;
removing the conductive capping layer and the recessed gate electrode layer of a first gate structure of the plurality of gate structures to form an opening;
forming an insulating material in the opening, wherein a top surface of the insulating material lower than a top surface of the gate dielectric layer and a top surface of the gate spacer of the first gate structure; and
forming a plurality of insulating capping layers over the plurality of gate structures, respectively, wherein a first insulating capping layer of the plurality of insulating capping layers is in the opening and covers the insulating material and a second insulating capping layer of the plurality of insulating capping layers covers the conductive capping layer of a second gate structure of the plurality of gate structures.
17 . The method as claimed in claim 16 , further comprising:
forming a source/drain feature in the substrate prior to formation of the gate structure, wherein the source/drain feature is adjacent to the gate structure; and
forming a contact structure over and electrically connected to the source/drain feature.
18 . The method as claimed in claim 17 , wherein a top surface of the contact structure is higher than the top surface of insulating material.
19 . The method as claimed in claim 17 , further comprising:
forming a via structure over and electrically connected to the contact structure.
20 . The method as claimed in claim 19 , wherein the via structure covers a top surface of the contact structure and a top surface of the first insulating capping layer.