Method for manufacturing for forming source/drain contact features and devices manufactured thereof
View Patent ↗The present disclosure relates to methods for forming self-aligned source/drain contacts with increased contact size while maintaining the reliability margin between source/drain contacts and gate electrodes. Semiconductor devices according to the present disclosure has contact landing Rc reduction at source/drain contacts as well as device performance improvement. The source/drain contacts formed according to the present disclosure also has lowered height leading to the capacitance reduction of between the source/drain contact to gate electrode. Embodiments of the present disclosure also provides improvements in circuit density and process margin. The self-aligned contact scheme according to the present disclosure allow more aggressive gate pitch (CPP) scaling and also maintain the landing area as well as contact-gate isolation margin.
1 . A method, comprising:
forming a fin structure along a first direction;
forming a sacrificial gate structure along a second direction and across the fin structure;
forming first and second sidewall spacers on opposing sidewalls of the sacrificial gate structure;
forming first and second source/drain regions on opposing sidewalls of the sacrificial gate structure;
depositing a contact etch stop layer over the first and second source/drain regions;
depositing a first dielectric layer on the contact etch stop layer;
forming a gate electrode layer, wherein forming the gate electrode layer comprises:
etching back a portion of the first and second sidewall spacers,
removing the sacrificial gate structure, and
depositing a gate electrode material layer, wherein the gate electrode layer has a T-shape profile; and
forming first and second source/drain contacts on the first and second source/region regions, wherein a top surface of the gate electrode layer is coplanar with top surfaces of the first and second source/drain contacts.
2 . The method of claim 1 , wherein forming the first and second source/drain contacts comprises:
forming first and second source/drain contact openings by etching the first dielectric layer using the gate electrode layer as a mask;
forming the first and second source/drain contacts in the first and second source/drain contact openings; and
performing a planarization process to expose the first and second sidewall spacers.
3 . The method of claim 2 , further comprising:
forming a gate end dielectric feature, wherein the gate end dielectric feature is in contact with the first source/drain contact.
4 . The method of claim 3 , wherein the gate end dielectric feature extends into a shallow trench isolation layer.
5 . The method of claim 1 , further comprising:
forming a butt contact on the top surface of the gate electrode layer and the top surface of the first source/drain contact.
6 . A method, comprising:
receiving a precursor structure comprising:
an active region comprising a channel region and a source/drain region,
a gate structure disposed over the channel region and comprising a lower portion and an upper portion, wherein the gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer, the gate electrode comprises a titanium-containing material;
a gate spacer disposed along a sidewall of the lower portion of the gate structure, wherein the gate electrode in the upper portion of the gate structure extends over the gate spacer,
a source/drain feature disposed over the source/drain region,
a contact etch stop layer (CESL) disposed over the source/drain feature, and
an interlayer dielectric (ILD) layer disposed over the CESL;
forming a mask over the precursor structure, the mask comprising an opening exposing the gate structure and a portion of the CESL and ILD layer over the source/drain feature;
selectively removing the exposed portion of the ILD layer; and
forming a source/drain contact over the source/drain feature.
7 . The method of claim 6 , wherein the forming of the source/drain contact comprises:
after the selectively removing of the exposed portion of the ILD layer, depositing a conductive material over the precursor structure; and
performing a planarization process to the precursor structure and the conductive material.
8 . The method of claim 7 , wherein the performing of the planarization process removes the upper portion of the gate structure.
9 . The method of claim 7 , wherein, after the performing of the planarization process, a top surface of the gate structure is coplanar with a top surface of the source/drain contact and a top surface of the gate spacer.
10 . The method of claim 6 , wherein the channel region comprises a plurality of nanostructures.
11 . The method of claim 10 , wherein the gate structure further comprises an inner portion wrapping around the plurality of nanostructures, and the precursor structure further comprises inner spacer features disposed between the inner portion of the gate structure and the source/drain feature.
12 . The method of claim 11 , wherein a dielectric constant of a material of the inner spacer features is greater than a dielectric constant of a material of the gate spacer.
13 . The method of claim 6 , further comprising:
forming a gate isolation structure configured to cut the gate structure into two segments, wherein a dielectric constant of a material of the gate isolation structure is greater than a dielectric constant of a material of the gate spacer.
14 . A method, comprising:
forming a dummy gate stack over a channel region;
forming a gate spacer extending along a sidewall of the dummy gate stack;
forming a contact etch stop layer (CESL) adjacent to the gate spacer; and
forming an interlayer dielectric (ILD) layer over the CESL;
after the forming of the ILD layer, removing an upper portion of the gate spacer to form a recess;
after the etching of the gate spacer, removing the dummy gate stack to form a trench;
forming a gate structure in the recess and the trench, the gate structure extending over the gate spacer; and
forming a conductive feature extending through the ILD layer and the CESL.
15 . The method of claim 14 , further comprising:
forming a source/drain feature coupled to the channel region; and
forming an isolation feature adjacent to a lower portion of the channel region.
16 . The method of claim 15 , wherein the ILD layer comprises a first portion over the source/drain feature and a second portion over the isolation feature, and wherein the forming of the conductive feature comprises:
forming a mask comprising an opening exposing the gate structure and the first portion of the ILD layer;
selectively removing the first portion of the ILD layer to expose the source/drain feature;
depositing a conductive material layer over the source/drain feature; and
performing a planarization process to expose the gate spacer.
17 . The method of claim 16 , wherein the conductive material layer is vertically spaced apart from the gate spacer by the gate structure.
18 . The method of claim 15 , further comprising:
removing a portion of the CESL under the first portion of the ILD layer and on the source/drain feature.
19 . The method of claim 14 , wherein the channel region comprises a plurality of nanostructures.
20 . The method of claim 13 , wherein in a cross-sectional view, a portion of the source/drain contact laterally extends into the gate isolation structure.