Adaptive memory management and control circuitry
An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.
1 . Resistive memory comprising:
a resistive memory array; and
an adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with extended test, reliability, performance or power optimizing capabilities, wherein the AMMC is configured with the power optimizing capabilities by having a first region of the resistive memory array active and having a second region of the resistive memory in a low power mode.
2 . The resistive memory of claim 1 , wherein the AMMC is integrated with the resistive memory array, wherein the low power mode comprises a Sleep mode or Deep Sleep mode.
3 . The resistive memory of claim 1 , wherein the AMMC is configured to adaptively enable the resistive memory to read and write dynamically from different regions inside the resistive memory.
4 . The resistive memory of claim 1 , further comprising:
a memory mapped interface to map adaptive memory management and control features to a memory mapped region of the resistive memory.
5 . The resistive memory of claim 1 , wherein the AMMC includes built-in self test circuitry to test functionality of the resistive memory array that is extended to additional testing functions.
6 . The resistive memory of claim 1 , wherein the resistive memory array comprises non-volatile random access memory (RAM) including one or more of magnetic RAM (MRAM), resistive RAM (RRAM), phase-change RAM (PCRAM), or Ferroelectric RAM (FeRAM).
7 . A memory subsystem comprising:
a smart compute memory circuitry;
a resistive memory array coupled to the smart compute memory circuitry; and
an Adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with the power optimizing capabilities by having a first region of the resistive memory array active and having a second region of the resistive memory in a low power mode.
8 . The memory subsystem of claim 7 , wherein the smart compute memory circuitry comprises an integrated processor with power-management control and memory management control to augment memory management and control of the AMMC.
9 . The memory subsystem of claim 7 , wherein the integrated processor is configured with programmable memory management and control to optimize parameters with different modes including a first mode to manipulate data to encrypt or decrypt the data as needed and a second mode for writing or reading at different speeds to optimize power and performance over a temperature range.
10 . The memory subsystem of claim 7 , wherein the integrated processor is configured with programmable memory management and control to optimize parameters with different modes including a third mode to generate a custom sequence of read and write operations, and a fourth mode to generate a conditional read or write operation based on output from a logic function.
11 . The memory subsystem of claim 7 , wherein the AMMC is configured to adaptively enable the resistive memory to read and write dynamically from different regions inside the resistive memory.
12 . The memory subsystem of claim 9 , wherein the integrated processor is configured to execute test code for the BIST circuitry with the test code being stored in a first region of the resistive memory array while a second region of the resistive memory array is being tested.
13 . The memory subsystem of claim 11 , wherein the low power mode comprises a Sleep mode or Deep Sleep mode.
14 . The memory subsystem of claim 7 , wherein the resistive memory array comprises non-volatile random access memory (RAM) including one or more of magnetic RAM (MRAM), resistive RAM (RRAM), phase-change RAM (PCRAM), or Ferroelectric RAM (FeRAM).
15 . Resistive memory comprising:
a resistive memory array; and
an adaptive Memory Management and Control circuitry (AMMC) coupled to the resistive memory array, wherein the AMMC is configured with a performance optimization mode to improve performance by reading from or writing to multiple memory banks of the resistive memory either sequentially or with a set addressing sequence enabling to read from or write to a second memory bank while a read or write settles in a first memory bank of the resistive memory.
16 . The resistive memory of claim 15 , wherein the AMMC is integrated with the resistive memory array.
17 . The resistive memory of claim 15 , wherein the AMMC is configured to adaptively enable the resistive memory to read and write dynamically from different regions inside the resistive memory.
18 . The resistive memory of claim 15 , further comprising:
a memory mapped interface to map adaptive memory management and control features to a memory mapped region of the resistive memory.
19 . The resistive memory of claim 15 , wherein the AMMC includes built-in self test circuitry to test functionality of the resistive memory array that is extended to additional testing functions.
20 . The resistive memory of claim 15 , wherein the resistive memory array comprises non-volatile random access memory (RAM) including one or more of magnetic RAM (MRAM), resistive RAM (RRAM), phase-change RAM (PCRAM), or Ferroelectric RAM (FeRAM).