Three-dimensional memory device containing dummy stack edge seal structure and methods for forming the same
A memory die includes first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks, memory opening fill structures located the first and second memory-region alternating stacks, and a peripheral alternating stack of peripheral insulating layers and spacer material which is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack. Bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance, and bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance.
1 . A semiconductor structure comprising a memory die, wherein the memory die comprises:
first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks;
memory openings vertically-extending through the first and second memory-region alternating stacks;
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements;
a peripheral alternating stack of peripheral insulating layers and spacer material layers having a different composition from the electrically conductive layers, the peripheral alternating stack is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack;
interconnect-level dielectric material layers embedding metal interconnect structures and overlying the first and second memory-region alternating stacks and the peripheral alternating stack; and
at least one edge seal wall structure comprising a respective set of at least one metal wall structure and a respective subset of the metal interconnect structures, and which continuously extends from a bottommost layer within the peripheral alternating stack to a horizontal plane including a top surface of the interconnect-level dielectric material layers
wherein:
bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance; and
bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance.
2 . The semiconductor structure of claim 1 , wherein each metal wall structure within the respective set of at least one metal wall structure laterally extends around the first and the second memory-region alternating stacks as a single continuous structure.
3 . The semiconductor structure of claim 1 , wherein the at least one edge seal wall structure comprises a nested plurality of edge seal wall structures within which each edge seal wall structure is laterally surrounded by, or laterally surrounds, any other edge seal wall structure within the nested plurality of edge seal wall structures.
4 . The semiconductor structure of claim 2 , wherein the nested plurality of edge seal wall structures comprises:
a first edge seal wall structure that vertically extends through a subset of all layers within the peripheral alternating stack and through a region of the second portion of the retro-stepped dielectric structure; and
a second edge seal wall structure that vertically extends through all layers within the peripheral alternating stack and is laterally spaced from the second portion of the retro-stepped dielectric structure.
5 . The semiconductor structure of claim 1 , A semiconductor structure comprising a memory die, wherein the memory die comprises:
first and second memory-region alternating stacks of memory-region insulating layers and electrically conductive layers that are laterally spaced apart from each other by a respective first portion of a retro-stepped dielectric structure overlying first stepped surfaces of the first and second memory-region alternating stacks;
memory openings vertically-extending through the first and second memory-region alternating stacks;
memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective vertical stack of memory elements; and
a peripheral alternating stack of peripheral insulating layers and spacer material layers having a different composition from the electrically conductive layers, the peripheral alternating stack is laterally spaced from the second memory-region alternating stack by a second portion of the retro-stepped dielectric structure overlying second stepped surfaces of the second memory-region alternating stack;
wherein:
bottom surfaces of the first and second memory-region alternating stacks are spaced apart by a first lateral spacing distance;
bottom surfaces of the second memory alternating stack and the peripheral alternating stack are spaced apart by the first lateral spacing distance;
the first memory-region alternating stack comprises a first memory plane;
the second memory-region alternating stack comprises a second memory plane;
the spacer material layers comprise dielectric material layers; and
the peripheral alternating stack comprises a dummy alternating stack.
6 . The semiconductor structure of claim 5 , wherein:
the dummy alternating stack comprises a dummy staircase region containing dummy stepped surfaces;
first stepped surfaces of the first and second memory-region alternating stacks and the second stepped surfaces of the second memory-region alternating stack comprise active staircase regions; and
an average horizontal step width of the first stepped surfaces of the first and second memory-region alternating stacks is the same as an average horizontal step width of the second stepped surfaces of the memory-region alternating stacks, and is the same as an average horizontal step width of the dummy stepped surfaces of the dummy alternating stack.
7 . The semiconductor structure of claim 5 , wherein:
the dummy alternating stack comprises a substantially straight sidewall;
the second stepped surfaces of the second memory-region alternating stack comprise an active staircase region; and
the bottom surface of an edge of a bottom step of the active staircase region of the second memory alternating stack and the bottom surface of the substantially straight sidewall of the peripheral alternating stack are spaced apart by the first lateral spacing distance.
8 . The semiconductor structure of claim 5 , wherein:
each first portion of the retro-stepped dielectric structure has a respective uniform bottom width between a pair of straight edges of a respective bottom surface, and has a respective uniform top width between a pair of straight edges of a respective top surface; and
the second portion of the retro-stepped dielectric structure has a second uniform bottom width that is the same as the respective uniform bottom width, and has a second uniform top width that is less than the respective uniform top width.
9 . The semiconductor structure of claim 8 , wherein:
the peripheral alternating stack comprises a vertical stack of a first-tier vertically alternating sequence and a second-tier vertically alternating sequence contacting a top surface of the first-tier vertically alternating sequence; and
a bottommost layer within the second-tier vertically alternating sequence has a greater lateral extent than a topmost layer of the first-tier vertically alternating sequence.
10 . The semiconductor structure of claim 8 , further comprising a dielectric frame laterally surrounding the peripheral alternating stack.
11 . The semiconductor structure of claim 8 , further comprising a logic die bonded to the memory die.