Memory device
A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.
1 . A memory device comprising a cell array, the cell array comprising:
a first sub cell array including a first memory cell and a second memory cell; and
a second sub cell array including a third memory cell,
wherein the first memory cell includes a first transistor, the second memory cell includes a second transistor, and the third memory cell includes a third transistor,
wherein the second transistor is closest to the first transistor among the other transistors in the first sub cell array, and the third transistor is closest to the second transistor among the other transistors in the second sub cell array,
wherein a shortest distance between a gate electrode of the second transistor and a gate electrode of the third transistor is larger than a shortest distance between a gate electrode of the first transistor and the gate electrode of the second transistor,
wherein the first transistor, the second transistor, and the third transistor are connected to a same word line, and
wherein the shortest distance between the gate electrode of the second transistor and the gate electrode of the third transistor is 3.5 μm or less.
2 . The memory device according to claim 1 , wherein each of the first transistor, the second transistor, and the third transistor includes a first oxide layer, a second oxide layer over the first oxide layer, a source electrode and a drain electrode over the second oxide layer, a third oxide layer between the source electrode and the drain electrode, a first insulating layer over the third oxide layer, and a first conductive layer over the first insulating layer.
3 . The memory device according to claim 2 , further comprising a second conductive layer below the first oxide layer.
4 . The memory device according to claim 1 , wherein a retention potential of each of the first memory cell, the second memory cell, and the third memory cell is 0.6 V or higher.
5 . The memory device according to claim 1 , wherein the shortest distance between the gate electrode of the first transistor and the gate electrode of the second transistor is 2.5 μm or less.
6 . A memory device comprising a cell array, the cell array comprising:
a first sub cell array including a first memory cell and a second memory cell;
a second sub cell array including a third memory cell; and
a dummy memory cell provided between the second memory cell and the third memory cell,
wherein the first memory cell includes a first transistor, the second memory cell includes a second transistor, and the third memory cell includes a third transistor,
wherein the second transistor is closest to the first transistor among the other transistors in the first sub cell array, and the third transistor is closest to the second transistor among the other transistors in the second sub cell array,
wherein a shortest distance between a gate electrode of the second transistor and a gate electrode of the third transistor is larger than a shortest distance between a gate electrode of the first transistor and the gate electrode of the second transistor,
wherein the first transistor, the second transistor, and the third transistor are connected to a same word line, and
wherein the shortest distance between the gate electrode of the second transistor and the gate electrode of the third transistor is 3.5 μm or less.
7 . The memory device according to claim 6 , wherein each of the first transistor, the second transistor, and the third transistor includes a first oxide layer, a second oxide layer over the first oxide layer, a source electrode and a drain electrode over the second oxide layer, a third oxide layer between the source electrode and the drain electrode, a first insulating layer over the third oxide layer, and a first conductive layer over the first insulating layer.
8 . The memory device according to claim 7 , further comprising a second conductive layer below the first oxide layer.
9 . The memory device according to claim 6 , wherein a retention potential of each of the first memory cell, the second memory cell, and the third memory cell is 0.6 V or higher.
10 . The memory device according to claim 6 , wherein the shortest distance between the gate electrode of the first transistor and the gate electrode of the second transistor is 2.5 μm or less.