Techniques for operating hybrid blocks in a memory device

1 . A method of performing an operation in a memory device, comprising the steps of:

preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the memory block being able to program and erase data according to both a one bit per memory cell (SLC) storage scheme and a multiple bits per memory cell storage scheme;

receiving a command to write data to the memory cells of the memory block in the multiple bits per memory cell storage scheme;

performing a sensing operation on a selected word line in the memory block using at least one reference voltage to determine if data stored in the memory block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme;

in response to a determination that the data contained in the memory block is in the SLC storage scheme, pre-programming the memory cells of the memory block and then erasing the memory cells; and

in response to a determination that the data contained in the memory block is in the multiple bits per memory cell storage scheme, erasing the memory cells without pre-programming the memory cells.

2 . The method as set forth in claim 1 , wherein after the step of erasing the memory cells, the method further includes the step of programming the memory cells of the memory block according to the multiple bits per memory cell storage scheme.

3 . The method as set forth in claim 2 , further including the step of continuously tracking and saving in the memory device which of the SLC storage scheme and the multiple bits per memory cell storage scheme data in the memory block is stored in.

4 . The method as set forth in claim 3 , wherein the step of performing the sensing operation on the selected word line using at least one reference voltage to determine if the data stored in the memory block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme includes performing the sensing operation using a two different reference voltage and counting a number of memory cells in the selected word line that have threshold voltages that are between the two different reference voltages to establish a count.

5 . The method as set forth in claim 4 , further including the steps of:

comparing the count to a predetermined threshold,

determining that the data stored in the memory block is in the SLC storage scheme in response to the count being below the predetermined threshold, and

determining that the data stored in the memory block is in the multiple bits per memory cell storage scheme in response to the count being above the predetermined threshold.

6 . The method as set forth in claim 2 , wherein the at least one reference voltage is a single reference voltage, and wherein the step of performing the sensing operation on the selected word line using the single reference voltage to determine if the data stored in the memory block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme includes:

counting a number of memory cells in the selected word line that have threshold voltages that are above the single reference voltage or counting a number of memory cells in the selected word line that have threshold voltages that are below the single reference voltage to establish a count, and

comparing the count to a predetermined threshold.

7 . The method as set forth in claim 6 , wherein the multiple bits per memory cell storage scheme is a three bits per memory cell (TLC) storage scheme.

8 . The method as set forth in claim 7 , wherein the single reference voltage is associated with a first programmed data state S1 of the TLC storage scheme.

9 . The method as set forth in claim 7 , wherein the single reference voltage is associated with a seventh programmed data state S7 of the TLC storage scheme.

10 . A memory device, comprising:

a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the memory block being configured to program and erase data according to both a one bit per memory cell (SLC) storage scheme and a multiple bits per memory cell storage scheme;

control circuitry configured to;

receive a command to write data to the memory cells of the memory block in the multiple bits per memory cell storage scheme,

perform a sensing operation on a selected word line in the memory block using at least one reference voltage to determine if data stored in the memory block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme,

in response to a determination that the data contained in the memory block is in the SLC storage scheme, pre-program the memory cells of the memory block and then erase the memory cells, and

in response to a determination that the data contained in the memory block is in the multiple bits per memory cell storage scheme, erase the memory cells without pre-programming the memory cells.

11 . The memory device as set forth in claim 10 , wherein after erasing the memory cells, the control circuitry is configured to program the memory cells of the memory block according to the multiple bits per memory cell storage scheme.

12 . The memory device as set forth in claim 11 , wherein the control circuitry is further configured to continuously track and save in the memory device which of the SLC storage scheme and the multiple bits per memory cell storage scheme data in the memory block is stored in.

13 . The memory device as set forth in claim 11 , wherein the at least one reference voltage is a single reference voltage and wherein when performing the sensing operation on the selected word line of the plurality of word lines to determine if the data stored in the memory block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme, the control circuitry is configured to:

either count a number of memory cells in the selected word line that have threshold voltages that are above the single reference voltage or count a number of memory cells in the selected word line that have threshold voltages that are below the single reference voltage to establish a count, and

compare the count to a predetermined threshold.

14 . The memory device as set forth in claim 13 , wherein the multiple bits per memory cell storage scheme is a three bits per memory cell (TLC) storage scheme.

15 . The memory device as set forth in claim 14 , wherein the single reference voltage is associated with a first programmed data state S1 of the TLC storage scheme.

16 . The memory device as set forth in claim 14 , wherein the single reference voltage is associated with a seventh programmed data state S7 of the TLC storage scheme.

17 . The memory device as set forth in claim 12 , wherein when performing the sensing operation on the selected word line using at least one reference voltage to determine if the data stored in the memory block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme, the control circuitry is configured to perform a sensing operation on a selected word line in the memory block using two different reference voltages and count a number of memory cells in the selected word line that have threshold voltages that are between the two different reference voltages to establish a count.

18 . The memory device as set forth in claim 17 , wherein the control circuitry is further configured to:

compare the count to a predetermined threshold,

determine that the data stored in the memory block is in the SLC storage scheme in response to the count being below the predetermined threshold, and

determine that the data stored in the memory block is in the multiple bits per memory cell storage scheme in response to the count being above the predetermined threshold.

19 . An apparatus, comprising:

a hybrid block that includes an array of memory cells that are arranged in a plurality of word lines, the hybrid block being configured to program and erase data according to both a one bit per memory cell (SLC) storage scheme and a three bits per memory cell (TLC) storage scheme;

a programming and erasing means configured to;

receive a command to write data to the memory cells of the hybrid block in the multiple bits per memory cell storage scheme,

perform a sensing operation on a selected word line in the hybrid block using at least one reference voltage to determine if data stored in the hybrid block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme,

in response to a determination that the data contained in the hybrid block is in the SLC storage scheme, pre-program the memory cells of the memory block and then erase the memory cells, and

in response to a determination that the data contained in the hybrid block is in the multiple bits per memory cell storage scheme, erase the memory cells without pre-programming the memory cells.

20 . The apparatus as set forth in claim 19 , wherein the at least one reference voltage is a single reference voltage and wherein when performing the sensing operation on the selected word line using the single reference voltage to determine if the data stored in the memory block is in the SLC storage scheme or is in the multiple bits per memory cell storage scheme, the programming and erasing means is configured to:

either count a number of memory cells in the selected word line that have threshold voltages that are above the single reference voltage or count a number of memory cells in the selected word line that have threshold voltages that are below the single reference voltage to establish a count, and

compare the count to a predetermined threshold.