IP Library › Granted Patent US 12,621,994
Granted Patent B2
US 12,621,994 · App. 18/319,260 · Granted May 5, 2026

Semiconductor device and manufacturing method of semiconductor device

Inventors: Chul Young Kim (Icheon-si, KR); Ji Yeon Baek (Icheon-si, KR); Kyung Sung Yun (Icheon-si, KR); Kyung Jin Lee (Icheon-si, KR); Sul Gi Jung (Icheon-si, KR)
Assignee: SK hynix Inc.
H10B43/27H10B41/10H10B41/27H10B43/10
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Quick Facts
Patent No.
US 12,621,994
App. No.
18/319,260
Granted
May 5, 2026
Kind
B2
Abstract

A semiconductor device includes: a first gate structure including a cell region and a contact region; a channel structure located in the cell region of the first gate structure; and a supporter located in the contact region of the first gate structure.

Claims (76)

1 . A semiconductor device comprising:

a first gate structure including a cell region and a contact region;

a channel structure located in the cell region of the first gate structure; and

a supporter located in the contact region of the first gate structure,

wherein the supporter comprises:

a first oxide layer;

a first nitride layer in the first oxide layer; and

a second oxide layer in the first nitride layer, and

wherein the supporter comprises a bowing shape.

2 . The semiconductor device of claim 1 , wherein the second oxide layer includes a void therein.

3 . The semiconductor device of claim 1 , wherein the supporter has a first width at a first level, has a second width at a second level, and has a third width at a third level located between the first level and the second level, the third width being greater than the first width and the second width.

4 . The semiconductor device of claim 1 , wherein the supporter has substantially at least one of a circular shape, an elliptical shape, a polygonal shape, and a line shape in a plane.

5 . The semiconductor device of claim 1 , further comprising:

a second gate structure; and

a slit structure located between the first gate structure and the second gate structure,

wherein the slit structure comprises:

a third oxide layer;

a second nitride layer in the third oxide layer; and

a fourth oxide layer in the second nitride layer, and

wherein the slit structure extends from the cell region to the contact region.

6 . The semiconductor device of claim 5 , wherein the slit structure has a bowing shape in a cross section.

7 . The semiconductor device of claim 5 , wherein at least one of the third oxide layer, the second nitride layer, and the fourth oxide layer includes a protrusion on an outer wall thereof.

8 . The semiconductor device of claim 5 , wherein the slit structure includes a source contact plug located in the fourth oxide layer.

9 . The semiconductor device of claim 8 , wherein the source contact plug includes a void therein.

10 . A semiconductor device comprising:

a first gate structure including a cell region and a contact region;

a channel structure located in the cell region of the first gate structure; and

a supporter located in the contact region of the first gate structure,

wherein the supporter comprises:

a first sealing layer;

a first stressor in the first sealing layer; and

a second sealing layer in the first stressor, and

wherein the supporter has a first width at a first level, has a second width at a second level, and has a third width at a third level located between the first level and the second level, the third width being greater than the first width and the second width.

11 . The semiconductor device of claim 10 , wherein the first stressor includes nitride, a low-k material, or a high-k material, or a combination thereof.

12 . The semiconductor device of claim 10 , wherein the first stressor includes silicon carbon nitride (SiCN), silicon boron nitride (SiBN), boron nitride (BN), aluminum oxide (AlO x ), or hafnium oxide (HfO x ), or a combination thereof.

13 . A semiconductor device, comprising:

a first gate structure including a cell region and a contact region;

a channel structure located in the cell region of the first gate structure; and

a supporter located in the contact region of the first gate structure,

wherein the supporter comprises:

a first sealing layer;

a first stressor in the first sealing layer; and

a second sealing layer in the first stressor, and

wherein the first sealing layer has a greater thickness than the second sealing layer.

14 . A semiconductor device, comprising:

a first gate structure including a cell region and a contact region;

a channel structure located in the cell region of the first gate structure; and

a supporter located in the contact region of the first gate structure,

wherein the supporter comprises:

a first sealing layer;

a first stressor in the first sealing layer; and

a second sealing layer in the first stressor;

a second gate structure; and

a slit structure located between the first gate structure and the second gate structure,

wherein the slit structure comprises:

a first insulating layer;

a second stressor in the first insulating layer; and

a second insulating layer in the second stressor, and

wherein the slit structure extends from the cell region to the contact region.

15 . The semiconductor device of claim 14 , wherein the slit structure includes a source contact plug located in the second insulating layer.

16 . The semiconductor device of claim 14 , wherein at least one of the first insulating layer, the second stressor, and the second insulating layer includes a protrusion on an outer wall thereof.

17 . A manufacturing method of a semiconductor device, the manufacturing method comprising:

forming a stack including a cell region and a contact region;

forming a first opening having a bowing shape in the contact region of the stack; and

forming, in the first opening, a supporter including a first oxide layer, a first nitride layer, and a second oxide layer.

18 . The manufacturing method of claim 17 , wherein the forming of the supporter comprises:

forming the first oxide layer in the first opening;

forming the first nitride layer in the first oxide layer; and

forming the second oxide layer in the first nitride layer.

19 . The manufacturing method of claim 18 , wherein the second oxide layer includes a void therein.

20 . The manufacturing method of claim 17 , further comprising:

forming, in the stack, a second opening extending from the cell region to the contact region and having a bowing shape; and

forming, in the second opening, a slit structure including a third oxide layer, a second nitride layer in the third oxide layer, and a fourth oxide layer in the second nitride layer.

21 . The manufacturing method of claim 20 , wherein the forming of the slit structure comprises:

forming a source contact plug in the fourth oxide layer.

22 . The manufacturing method of claim 21 , wherein the source contact plug includes a void therein.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2023
From: KIM, CHUL YOUNG; BAEK, JI YEON; YUN, KYUNG SUNG; LEE, KYUNG JIN; JUNG, SUL GI
To: SK HYNIX INC.
Reel/Frame 063676/0286 →
Priority Claims (1)
KR 10-2022-0172779 · Dec 12, 2022 · national
Continuity (1)
Related Publication 20240196608A1 · Jun 13, 2024
References Cited (11)
US 10103236B2 · Lim · 2018 [cited by examiner]
US 11688689B2 · Jhothiraman · 2023 [cited by examiner]
US 20170278860A1 · Aoyama · 2017 [cited by examiner]
US 20180277562A1 · Umezawa · 2018 [cited by examiner]
US 20190326315A1 · Lee · 2019 [cited by examiner]
US 20210082952A1 · Fukumoto · 2021 [cited by examiner]
US 20210249434A1 · Nishikawa · 2021 [cited by examiner]
US 20210358868A1 · Jhothiraman et al. · 2021 [cited by applicant]
US 20220052068A1 · Kawaguchi · 2022 [cited by examiner]
US 20220115335A1 · Kothari et al. · 2022 [cited by applicant]
US 20220310505A1 · Hama · 2022 [cited by examiner]