Memory cell with a buffer layer and its fabrication process
View Patent ↗Some embodiments relate to an integrated chip including a bottom electrode over a semiconductor substrate. A seed layer overlies the bottom electrode. A data storage structure is arranged on the seed layer. A first buffer layer is arranged between the bottom electrode and the seed layer. The first buffer layer is in physical contact with the seed layer and opposing sidewalls of the first buffer layer are aligned with opposing sidewalls of the seed layer.
1 . An integrated chip, comprising:
a bottom electrode overlying a semiconductor substrate;
a seed layer over the bottom electrode;
a data storage structure arranged on the seed layer; and
a first buffer layer between the bottom electrode and the seed layer, wherein the first buffer layer is in physical contact with the seed layer, and wherein opposing sidewalls of the first buffer layer are aligned with opposing sidewalls of the seed layer;
a top electrode overlying the data storage structure; and
a second buffer layer arranged between the data storage structure and the top electrode, wherein the first buffer layer and the second buffer layer respectively comprise an amorphous non-magnetic material.
2 . The integrated chip of claim 1 , wherein the amorphous non-magnetic material of the first buffer layer comprises an alloy of a first metal and a second metal, wherein the first metal is iron or cobalt and the second metal is hafnium, yttrium, or zirconium.
3 . The integrated chip of claim 2 , wherein a first atomic percentage of the first metal in the first buffer layer is greater than a second atomic percentage of the second metal in the first buffer layer.
4 . The integrated chip of claim 3 , wherein the second atomic percentage is within a range of 18 to 40.
5 . The integrated chip of claim 1 , wherein an upper surface of the first buffer layer is substantially planar and an upper surface of the bottom electrode has a saw-toothed profile.
6 . The integrated chip of claim 1 , wherein the data storage structure comprises a hard bias stack on the seed layer, a reference layer on the hard bias stack, a barrier layer on the reference layer, and a free layer on the barrier layer.
7 . The integrated chip of claim 1 , further comprising:
a third buffer layer arranged between the seed layer and the data storage structure, wherein the third buffer layer comprises the amorphous non-magnetic material.
8 . The integrated chip of claim 1 , further comprising:
a first insulator arranged along a first sidewall of the bottom electrode; and
a second insulator arranged along a second sidewall of the bottom electrode, wherein widths of the first and second insulators are less than a width of the bottom electrode.
9 . The integrated chip of claim 8 , wherein the widths of the first and second insulators continuously decrease from top surfaces of the first and second insulators in a first direction towards the semiconductor substrate, and wherein the width of the bottom electrode continuously increases from a bottom surface of the bottom electrode in a second direction opposite the first direction.
10 . An integrated chip, comprising:
a conductive interconnect over a semiconductor substrate;
a memory cell over the conductive interconnect, wherein the memory cell comprises:
a bottom electrode on the conductive interconnect;
a hard bias stack on the bottom electrode and having a first crystalline structure and a first orientation;
a reference layer on the hard bias stack;
a barrier layer on the reference layer;
a free layer on the barrier layer; and
a first diffusion barrier layer arranged between the bottom electrode and the hard bias stack, wherein the first diffusion barrier layer directly contacts a top surface of the bottom electrode, and wherein the first diffusion barrier layer has the first crystalline structure and the first orientation.
11 . The integrated chip of claim 10 , further comprising:
a second diffusion barrier layer arranged between the bottom electrode and the conductive interconnect, wherein the second diffusion barrier layer comprises a planar top surface that directly contacts and extends along a bottom surface of the bottom electrode, and wherein the first diffusion barrier layer comprises a first material and the second diffusion barrier layer comprises a second material different from the first material.
12 . The integrated chip of claim 11 , wherein the second material comprises a diffusive species and wherein the first material is substantially free of the diffusive species.
13 . The integrated chip of claim 10 , further comprising:
an insulator structure arranged on opposing sides of the bottom electrode, wherein a top surface of the insulator structure is coplanar with the top surface of the bottom electrode, wherein in a top view the insulator structure comprises a body structure wrapped around a perimeter of the bottom electrode and a plurality of peripheral segments that branch off from the body structure in different directions, wherein a width of a first segment of the body structure is less than a width of the bottom electrode.
14 . The integrated chip of claim 10 , wherein the memory cell further comprises:
a seed layer between the first diffusion barrier layer and the hard bias stack, wherein the seed layer directly contacts a top surface of the first diffusion barrier layer, wherein a thickness of the seed layer is greater than a thickness of the first diffusion barrier layer, and wherein the seed layer and the first diffusion barrier layer are amorphous.
15 . The integrated chip of claim 14 , wherein a top surface of the seed layer and the top surface of the first diffusion barrier layer are substantially flat and different from the top surface of the bottom electrode.
16 . The integrated chip of claim 10 , wherein an average diameter of grains of the first diffusion barrier layer is less than 1 nanometer.
17 . An integrated chip, comprising:
a conductive interconnect over a substrate;
a first electrode over the conductive interconnect;
a diffusion barrier layer over an upper surface of the first electrode, wherein an upper surface of the diffusion barrier layer is substantially planar, wherein an average diameter of grains of the diffusion barrier layer is less than 1 nanometer;
a data storage structure over the diffusion barrier layer; and
a second electrode over the data storage structure.
18 . The integrated chip of claim 17 , wherein a lower surface of the diffusion barrier layer physically contacts the upper surface of the first electrode.
19 . The integrated chip of claim 17 , wherein outer sidewalls of the diffusion barrier layer are aligned with outer sidewalls of the second electrode and are spaced between outer sidewalls of the first electrode.
20 . The integrated chip of claim 17 , further comprising:
a seed layer between the diffusion barrier layer and the data storage structure, wherein a thickness of the seed layer is greater than a thickness of the diffusion barrier layer.