IP Library › Granted Patent US 12,635,189
Granted Patent B2
US 12,635,189 · App. 17/849,424 · Granted May 19, 2026

Semiconductor device and method of manufacturing thereof

Inventors: Wen-Yen Chen (Hsinchu, TW); Tsai-Yu Huang (Taoyuan, TW); Yee-Chia Yeo (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D30/797H10D30/601H10D64/251H10D30/6757
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Quick Facts
Patent No.
US 12,635,189
App. No.
17/849,424
Granted
May 19, 2026
Kind
B2
Abstract

A semiconductor device includes a field effect transistor disposed over a first main surface of a semiconductor substrate, a distributed Bragg reflector disposed over an opposing second main surface of the semiconductor substrate, and a conductive via disposed in the distributed Bragg reflector. The field effect transistor includes a gate structure and a source/drain region. The conductive via passes through the semiconductor substrate and is in direct electrical contact with the source/drain region. A metal silicide is formed in a portion of the source/drain region that is in contact with the conductive via, and thus can reduce contact resistance between the source/drain region and the conductive via. The source/drain region is laser annealed through an opening formed through the distributed Bragg reflector. The distributed Bragg reflector reduces or prevents thermal damage to other regions of the semiconductor device that are protected by the distributed Bragg reflector.

Claims (117)

1 . A method of manufacturing a semiconductor device, comprising:

forming a semiconductor device component over a first main surface of a semiconductor substrate, wherein the semiconductor device component includes an epitaxial layer;

forming a plurality of alternating first layers having a first refractive index and second layers having a second refractive index over an opposing second main surface of the semiconductor substrate, wherein the first refractive index and the second refractive index are different;

forming an opening in the plurality of first layers and second layers, and through the second main surface of the semiconductor substrate exposing a portion of the epitaxial layer through the opening;

implanting a dopant into the epitaxial layer to form a doped epitaxial layer via the opening; and

irradiating the doped epitaxial layer with laser radiation through the opening.

2 . The method of claim 1 , wherein:

a first thickness (d 1 ) of the first layers satisfies

d

1

=

λ

4

⁢

n

1

,

where λ is a wavelength of the laser radiation and n 1 is the first refractive index of the first layers,

a second thickness (d 2 ) of the second layers satisfies

d

2

=

λ

4

⁢

n

2

,

where n 2 is the second refractive index of the second layers, and

the wavelength (λ) of the laser radiation is in a range of 512 to 552 nm.

3 . The method of claim 1 , wherein the first layers comprise amorphous silicon, wherein the second layers comprise silicon oxide or silicon nitride.

4 . The method of claim 1 , wherein the epitaxial layer comprises SiGeB, and wherein implanting the dopant into the epitaxial layer comprises implanting Ge and B to amorphize the epitaxial layer and to increase B concentration in the doped epitaxial layer.

5 . The method of claim 1 , wherein the laser radiation radiates the doped epitaxial layer through the opening in a time range of 1 nano-second to 100 milli-seconds.

6 . The method of claim 4 , wherein the laser radiation radiates through the opening to heat the doped epitaxial layer to a temperature in a range of 600° C. to 1200° C.

7 . The method of claim 1 , further comprising:

depositing a conformal silicon nitride liner in the opening by atomic layer deposition; and

dry etching the silicon nitride liner from a bottom of the opening so that the silicon nitride liner remains on sides of the opening.

8 . The method of claim 1 , further comprising:

pre-silicide implanting a pre-silicide dopant into the epitaxial layer;

depositing a metal on the epitaxial layer; and

forming a metal silicide on the epitaxial layer.

9 . The method of claim 1 , further comprising:

filling the opening with a metal material, wherein the metal material is selected from a group consisting of W, Co, and Ru.

10 . The method of claim 9 , further comprising:

after filling the opening with the metal material, planarizing an outside surface of the plurality of the alternating first and second layers by a chemical mechanical polishing.

11 . A method of manufacturing a semiconductor device, comprising:

forming a field effect transistor over a first main surface of a wafer, wherein the field effect transistor includes a source/drain region;

forming a distributed Bragg reflector over an opposing second main surface of the wafer;

forming a via opening in the distributed Bragg reflector exposing a portion of the source/drain region;

implanting a dopant into the source/drain region to form a doped source/drain region; and

laser annealing the doped source/drain region using laser radiation.

12 . The method of claim 11 , wherein the distributed Bragg reflector comprises a plurality of alternating first layers having a first refractive index (n 1 ) and second layers having a second refractive index (n 2 ), wherein the first refractive index and the second refractive index are different.

13 . The method of claim 12 , wherein:

a first thickness (d 1 ) of the first layers satisfies

d

1

=

λ

4

⁢

n

1

,

where λ is a wavelength of the laser radiation and n 1 is the first refractive index of the first layers, and

a second thickness (d 2 ) of the second layers satisfies

d

2

=

λ

4

⁢

n

2

,

where n 2 is the second retractive index of the second layers.

14 . The method of claim 11 , further comprising:

after laser annealing the doped source/drain region, pre-silicide implanting a pre-silicide dopant into the source/drain region;

depositing a metal on the epitaxial layer; and

forming a metal silicide on the source/drain region.

15 . A method of manufacturing a semiconductor device, comprising:

forming a gate all around (GAA) field effect transistor (FET) over a first main surface of a semiconductor substrate, wherein the GAA FET includes an epitaxial layer;

forming a plurality of alternating amorphous silicon layers and silicon oxide layers over an opposing second main surface of the semiconductor substrate;

forming an opening in the plurality of alternating amorphous silicon layers and silicon oxide layers, and through the second main surface of the semiconductor substrate exposing a portion of the epitaxial layer through the opening;

implanting a dopant into the epitaxial layer to form a doped epitaxial layer via the opening;

irradiating the doped epitaxial layer with laser radiation through the opening; and

forming a metal silicide on the epitaxial layer.

16 . The method of claim 15 , wherein:

a first thickness (d 1 ) of the amorphous silicon layers satisfies

d

1

=

λ

4

⁢

n

1

,

where λ is a wavelength of the laser radiation and n 1 is a first refractive index of the amorphous silicon layers,

a second thickness (d 2 ) of the silicon oxide layers satisfies

d

2

=

λ

4

⁢

n

2

,

where n 2 is a second refractive index of the silicon oxide layers, and

the wavelength (λ) of the laser radiation is in a range of 512 to 552 nm.

17 . The method of claim 15 , further comprising:

depositing a conformal silicon nitride liner in the opening by atomic layer deposition; and

dry etching the silicon nitride liner from a bottom of the opening so that the silicon nitride liner remains on sides of the opening.

18 . The method of claim 15 , wherein:

the epitaxial layer comprises SiGeB, and implanting the dopant into the epitaxial layer comprises implanting Ge and B to amorphize the epitaxial layer and to increase B concentration in the doped epitaxial layer.

19 . The method of claim 15 , wherein the laser radiation radiates the doped epitaxial layer through the opening in a time range of 1 nano-second to 100 milli-seconds.

20 . The method of claim 19 , wherein the laser radiation radiates through the opening to heat the doped epitaxial layer to a temperature in a range of 600° C. to 1200° C.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2022
From: CHEN, WEN-YEN; HUANG, TSAI-YU; YEO, YEE-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060310/0923 →
Continuity (1)
Related Publication 20230420563A1 · Dec 28, 2023
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