Multi-gate device fabrication methods and related structures
A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.
1 . A method of fabricating a semiconductor device, comprising:
providing a fin extending from a substrate, wherein the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor;
forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor;
forming a P-type metal film surrounding the first gate dielectric layer;
after forming the P-type metal film, annealing the semiconductor device;
after the annealing, removing the P-type metal film; and
after removing the P-type metal film, forming a second gate dielectric layer surrounding the first gate dielectric layer.
2 . The method of claim 1 , wherein the P-type metal film includes at least one of Al, Ti, or N.
3 . The method of claim 1 , wherein the P-type metal film includes a first layer formed on the first gate dielectric layer, a second layer formed on the first layer, and a third layer formed on the second layer.
4 . The method of claim 3 , wherein the first layer includes AlN, the second layer includes TiAIN, and the third layer includes AlN.
5 . The method of claim 3 , wherein the second layer has a greater thickness than the first layer, and wherein the third layer has a greater thickness than the second layer.
6 . The method of claim 1 , wherein annealing the semiconductor device causes atoms from the P-type metal film to diffuse into the first gate dielectric layer and modulate a flatband voltage (Vfb) of the first gate dielectric layer to form a Vfb-modulated first gate dielectric layer.
7 . The method of claim 6 , wherein the first gate dielectric layer includes hafnium oxide (HfO x ), and wherein the Vfb-modulated first gate dielectric layer includes HfTiAlNO x .
8 . The method of claim 1 , wherein the first gate dielectric layer includes an interfacial layer (IL) and a first high-K dielectric layer disposed over the IL, wherein the second gate dielectric layer includes a second high-K dielectric layer disposed over the first high-K dielectric layer.
9 . The method of claim 1 , further comprising:
forming a P-type work-function metal (PWFM) layer surrounding the second gate dielectric layer.
10 . The method of claim 1 , wherein the P-type transistor includes a P-type gate-all-around (GAA) transistor or a P-type forksheet transistor.
11 . The method of claim 1 , wherein the annealing the semiconductor device includes annealing the semiconductor device using a rapid thermal anneal (RTA) process.
12 . A method, comprising:
providing a first fin in an N-type device region and a second fin in a P-type device region, wherein each of the first and second fins include a plurality of semiconductor channel layers;
forming a gate dielectric surrounding each of the plurality of semiconductor channel layers within each of the N-type device region and the P-type device region;
depositing a first metal film surrounding the gate dielectric in the P-type device region, wherein the first metal film includes at least Al;
performing a first annealing process to modulate a first flatband voltage (Vfb) of the gate dielectric in the P-type device region; and
removing the first metal film.
13 . The method of claim 12 , further comprising:
prior to depositing the first metal film, depositing a second metal film surrounding the gate dielectric in the N-type device region;
performing a second annealing process to modulate a second Vfb of the gate dielectric in the N-type device region; and
removing the second metal film.
14 . The method of claim 12 , wherein the first metal film further includes at least one of Ti or N.
15 . The method of claim 13 , wherein the second metal film includes La.
16 . The method of claim 12 , further comprising:
after removing the first metal film, forming a P-type work-function metal (PWFM) layer over the gate dielectric in the P-type device region and an N-type work-function metal (NWFM) layer over the gate dielectric in the N-type device region; and
forming an isolation layer that contacts each of the PWFM layer and the NWFM layer and that electrically isolates the first fin in the N-type device region from the second fin in the P-type device region.
17 . A method, comprising:
providing a P-type device in a P-type device region and an N-type device in an N-type device region, wherein each of the P-type device and the N-type device include a plurality of channel layers, and wherein the P-type device and the N-type device are electrically isolated from each other by a dielectric wall formed therebetween;
forming a dielectric layer on three sides of each of the plurality of channel layers of the P-type device and the N-type device;
depositing a metal film stack over the dielectric layer of the P-type device;
after performing an annealing process to modulate a flatband voltage (Vfb) of the P-type device, removing the metal film stack; and
after removing the metal film stack, forming an additional dielectric layer over the dielectric layer on the three sides of each of the plurality of channel layers of the P-type device and the N-type device.
18 . The method of claim 17 , wherein the metal film stack includes at least one of Al, Ti, or N.
19 . The method of claim 17 , further comprising:
after forming the additional dielectric layer, forming a P-type work-function metal (PWFM) layer over the additional dielectric layer of the P-type device and an N-type work-function metal (NWFM) layer over the additional dielectric layer of the N-type device.
20 . The method of claim 19 , further comprising:
forming a metal capping layer over each of the PWFM layer and the NWFM layer, where a top surface of the metal capping layer is level with a top surface of the dielectric wall.