Memory cell and semiconductor memory device with the same
Present invention relates to a semiconductor memory device. A semiconductor memory device according to the present invention may comprise: a memory cell array including a plurality of memory cells over a substrate, the plurality of memory cells repeatedly arranged in horizontal direction and a vertical direction, the horizontal direction parallel to a surface of the substrate, the vertical direction perpendicular to the surface of the substrate, a bit line coupled to the memory cells arranged in the vertical direction, and a word line coupled to the memory cells arranged in the horizontal direction, wherein each of the memory cells comprises a capacitor comprising a storage node and a plate node, and the plate nodes of the capacitors are coupled to each other in the vertical direction and are spaced apart from each other in the horizontal direction.
1 . A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells over a substrate, the plurality of memory cells repeatedly arranged in a horizontal direction and a vertical direction, the horizontal direction parallel to a surface of the substrate, the vertical direction perpendicular to the surface of the substrate;
a plurality of bit lines, each bit line coupled to some of the plurality of memory cells which are stacked and arranged in the vertical direction over the substrate; and
a plurality of word lines, each word line coupled to some of the plurality of memory cells arranged in the horizontal direction over the substrate,
wherein each memory cell comprises a capacitor and an active layer which are arranged in the horizontal direction over the substrate, the active layer coupled to the word line and the bit line,
wherein the capacitor comprises a bident-shaped storage node coupled to the active layer and a trident-shaped plate node coupled to a plate line arranged in the vertical direction over substrate,
wherein the bident-shaped storage node and the trident-shaped plate node are horizontally arranged over the substrate to interlock with each other, and
wherein the plate line is coupled to plate nodes of plural capacitors of plural memory cells arranged in the horizontal direction and the vertical direction.
2 . The semiconductor memory device of claim 1 , further including a capacitor isolation layer, the capacitor isolation layer being formed between the plate nodes of the capacitors of the row array.
3 . The semiconductor memory device of claim 1 , wherein the bident-shaped storage node further comprises a cylindrical storage node, and
wherein the bident-shaped storage node and the trident-shaped plate node face each other with a dielectric layer interposed therebetween.
4 . The semiconductor memory device of claim 1 , further comprising:
contact plugs connected to the plate nodes, respectively; and
a common plate line connected to the contact plugs.
5 . The semiconductor memory device of claim 1 , wherein the bident-shaped storage node of the capacitor is spaced apart from that of another capacitor in the horizontal direction and the vertical direction.
6 . The semiconductor memory device of claim 1 ,
wherein the active layer comprises a channel, the channel being parallel to the surface of the substrate, and
wherein the channel includes a thin-body channel thinner than the word line.
7 . The semiconductor memory device of claim 6 , wherein the word line includes a first word line and a second word line, the first word line and the second word line facing each other with the thin-body channel interposed therebetween.
8 . The semiconductor memory device of claim 6 ,
wherein the word line includes a single word line or a gate all around word line,
wherein the single word line is disposed on an upper surface or a lower surface of the thin-body channel, and
wherein the gate of all around word line surrounds the thin-body channel.
9 . The semiconductor memory device of claim 6 , wherein the channel includes a semiconductor material or an oxide semiconductor material.
10 . The semiconductor memory device of claim 6 , wherein the channel includes polysilicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide).
11 . The semiconductor memory device of claim 1 , wherein the memory cells include a Dynamic Random-Access Memory (DRAM) cell.
12 . The semiconductor memory device of claim 1 , further including a peripheral circuit for controlling the memory cells of the memory cell array.
13 . The semiconductor memory device of claim 12 ,
wherein the peripheral circuit is disposed at a lower level than the memory cell array, or
wherein the peripheral circuit is disposed at a higher level than the memory cell array.
14 . The semiconductor memory device of claim 1 , wherein each of the trident-shaped plate nodes of the capacitors comprises:
an inner node disposed inside the storage node;
outer nodes disposed between the storage nodes of the capacitors arranged along the horizontal direction; and
a body node disposed between the outer nodes and connected to the inner node.
15 . The semiconductor memory device of claim 1 ,
wherein the bit line is vertically oriented in the vertical direction, and
wherein the word line is horizontally oriented in the horizontal direction.
16 . A semiconductor device, comprising:
a plurality of memory cells, each memory cell comprising an active layer and a capacitor;
a word line arranged in a horizontal direction over a substrate; and
a bit line arranged in a vertical direction over a substrate, the active layer coupled to the word line and the bit line; and
a plate line arranged in the vertical direction over the substrate,
wherein the memory cells are arranged between the bit line and the plate line in the horizontal direction and the vertical direction over the substrate,
wherein the capacitor comprises a bident-shaped storage node, a trident-shaped plate node, and a dielectric layer between the bident-shaped storage node and the trident-shaped plate node coupled to the plate line, and
wherein the bident-shaped storage node and the trident-shaped plate node are horizontally arranged over the substrate to interlock with each other.
17 . The semiconductor device of claim 16 , further including a capacitor isolation layer, the capacitor isolation layer being formed between the trident-shaped plate nodes of the capacitors of the row array arranged along the horizontal direction.
18 . The semiconductor device of claim 16 , wherein the bident-shaped storage node further comprises a cylindrical storage node, and
wherein the bident-shaped storage node and the trident-shaped plate node face each other with a dielectric layer interposed therebetween.
19 . The semiconductor device of claim 16 , further comprising:
a plurality of contact plugs connected to the trident-shaped plate nodes, respectively; and
a common plate line connected to the plurality of contact plugs.
20 . The semiconductor device of claim 16 ,
wherein the bident-shaped storage node of the capacitor is spaced apart from that of another capacitor in the horizontal direction and the vertical direction.