Granted Patent B2

US 12,660,239 · App. 17/912,560 · Granted Jun 16, 2026

Inventors: Yusuke Negoro (Kaizuka, JP); Seiichi Yoneda (Isehara, JP); Shunpei Yamazaki (Setagaya, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H10D30/67H04N25/40

Abstract

Claims (53)

1 . An imaging device comprising a plurality of pixels and a plurality of first circuits,

wherein the plurality of pixels is arranged in a matrix,

wherein the first circuit is electrically connected to the plurality of pixels arranged in a column direction,

wherein one of the plurality of pixels comprises a second circuit and a third circuit,

wherein one of the second circuit and the third circuit is configured to generate first data of an n-th frame by supplying a first weight to image data obtained in the n-th frame,

wherein the other of the second circuit and the third circuit is configured to generate first data of an n−1-th frame by supplying a second weight to image data obtained in the n−1-th frame,

wherein the one of the plurality of pixels is configured to generate second data by adding the first data of the n−1-th frame and the first data of the n-th frame,

wherein the first circuit is configured to generate third data corresponding to a sum of the second data generated by the plurality of pixels, and

wherein n is an integer greater than or equal to 2.

2 . The imaging device according to claim 1 ,

wherein the one of the plurality of pixels comprises a photoelectric conversion device and a first transistor,

wherein the second circuit and the third circuit each comprise a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor,

wherein one electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor,

wherein the gate of the fourth transistor is electrically connected to one electrode of the first capacitor,

wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the fifth transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the first transistor, and

wherein the other of the source and the drain of the first transistor is electrically connected to the first circuit.

3 . The imaging device according to claim 2 ,

wherein the other of the source and the drain of the fifth transistor is electrically connected to a first wiring, and

wherein the first wiring is supplied with either a potential corresponding to the first weight or a potential corresponding to the second weight.

4 . The imaging device according to claim 1 ,

wherein the one of the plurality of pixels comprises a photoelectric conversion device and a first transistor,

wherein the second circuit and the third circuit each comprise a second transistor, a third transistor, a fourth transistor, and a first capacitor,

wherein one electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor,

wherein the gate of the fourth transistor is electrically connected to one electrode of the first capacitor,

wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to the first circuit, and

wherein the fourth transistor comprises a back gate.

5 . The imaging device according to claim 4 ,

wherein the back gate is electrically connected to a first wiring, and

wherein the first wiring is supplied with either a potential corresponding to the first weight or a potential corresponding to the second weight.

6 . The imaging device according to claim 1 ,

wherein the first circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a second capacitor,

wherein one electrode of the second capacitor is electrically connected to the plurality of pixels,

wherein the one electrode of the second capacitor is electrically connected to the sixth transistor,

wherein the other electrode of the second capacitor is electrically connected to one of a source and a drain of the seventh transistor,

wherein the one of the source and the drain of the seventh transistor is electrically connected to a gate of the eighth transistor,

wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor, and

wherein the one of the source and the drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor.

7 . The imaging device according to claim 1 ,

wherein at least one of the transistors of the one of the plurality of pixels and the transistors of the first circuit comprises a metal oxide in a channel formation region,

wherein the metal oxide comprises In, Zn, and an element M, and

wherein M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf.

8 . The imaging device according to claim 1 ,

wherein at least one of the transistors of the one of the plurality of pixels and the transistors of the first circuit comprises silicon in a channel formation region.

9 . The imaging device according to claim 1 ,

wherein one of the transistors of the one of the plurality of pixels and the transistors of the first circuit comprises a metal oxide in a channel formation region,

wherein a transistor different from the one of the transistors of the one of the plurality of pixels and the transistors of the first circuit comprises silicon in a channel formation region, and

wherein M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (77)