Semiconductor structure of hybrid cell array
A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.
1 . A semiconductor structure, comprising:
a cell array having a plurality of rows, and comprising:
a plurality of first logic cells arranged in at least one first row, wherein the first logic cells share a first active region; and
a plurality of second logic cells arranged in at least one second row, wherein each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by a first isolation structure,
wherein the first logic cells of the first row are in contact with the second logic cells of the second row;
wherein the first active region is a first continuous active region shared by first conductivity type transistors of the first logic cells, and the first conductivity type transistors of two adjacent first logic cells are separated from each other by a first dummy transistor;
wherein second conductivity type transistors of each of the first logic cells are formed in a discontinuous active region, and the discontinuous active regions of the two adjacent first logic cells are separated from each other by a second isolation structure;
wherein the second isolation structure is formed by performing a metal gate cutting process or a polysilicon cutting process on an extension of a gate structure of the first dummy transistor, and the second isolation structure extends above a top surface of the discontinuous active region.
2 . The semiconductor structure as claimed in claim 1 , wherein each of the second active regions is a first discontinuous active region, and first conductivity type transistors of each of the second logic cells are formed in respective first discontinuous active regions.
3 . The semiconductor structure as claimed in claim 2 , wherein second conductivity type transistors of each of the second logic cells are formed in a second discontinuous active region, and the second discontinuous active regions of the two adjacent second logic cells are separated from each other by the first isolation structure.
4 . The semiconductor structure as claimed in claim 2 , wherein second conductivity type transistors of the second logic cells share a continuous active region that is parallel to the first active region, and the second conductivity type transistors of the two adjacent second logic cells are separated from each other by a second dummy transistor.
5 . The semiconductor structure as claimed in claim 1 , wherein the first rows and the second rows have the same number, and the first and second rows are alternately arranged in the cell array.
6 . The semiconductor structure as claimed in claim 1 , wherein the number of the first rows is different from the number of the second rows in the cell array.
7 . The semiconductor structure as claimed in claim 1 , wherein in the second row, the number of the second logic cells is equal to the number of the second active regions.
8 . A semiconductor structure, comprising:
a cell array having a plurality of rows, wherein the rows are divided into a plurality of groups, and each of the groups comprises:
a plurality of first logic cells arranged in a first row, wherein first conductivity type transistors of the first logic cells share a first continuous active region, and second conductivity type transistors of each of the first logic cells are formed in a first discontinuous active region; and
a plurality of second logic cells arranged in a second row, wherein first conductivity type transistors of each of the second logic cells are formed in a second discontinuous active region, and second conductivity type transistors of the second logic cells share a second continuous active region,
wherein in the second row, the second discontinuous active regions of two adjacent second logic cells are separated from each other by a first isolation structure;
wherein in the first row, the first discontinuous active regions of two adjacent first logic cells are separated from each other by a second isolation structure, and the first conductivity type transistors of the two adjacent first logic cells are separated from each other by a first dummy transistor;
wherein the second isolation structure is formed by performing a metal gate cutting process or a polysilicon cutting process on an extension of a gate structure of the first dummy transistor, and the second isolation structure extends above a top surface of the first discontinuous active region.
9 . The semiconductor structure as claimed in claim 8 , wherein in the second row, the second conductivity type transistors of the two adjacent second logic cells are separated from each other by a second dummy transistor.
10 . The semiconductor structure as claimed in claim 8 , wherein the second continuous active region is parallel to the first continuous active region.
11 . The semiconductor structure as claimed in claim 8 , wherein the first discontinuous active regions in the first row are surrounded by the first continuous active region in the first row and the second continuous active region in the second row, and the second continuous active region in the second row is surrounded by the first discontinuous active regions in the first row and the second discontinuous active regions in the second row.
12 . The semiconductor structure as claimed in claim 8 , wherein the first continuous active region in the first row is surrounded by the first discontinuous active regions in the first row and the second discontinuous active regions in the second row, and the second discontinuous active regions in the second row are surrounded by the first continuous active region in the first row and the second continuous active region in the second row.
13 . The semiconductor structure as claimed in claim 8 , wherein in the first row, the number of the first logic cells is equal to the number of the first discontinuous active regions.
14 . The semiconductor structure as claimed in claim 8 , wherein in the second row, the number of the second logic cells is equal to the number of the second discontinuous active regions.
15 . The semiconductor structure as claimed in claim 8 , wherein each of the groups further comprises:
a plurality of third logic cells arranged in a third row, wherein the third logic cells share a third continuous active region.
16 . The semiconductor structure as claimed in claim 8 , wherein each of the groups further comprises:
a plurality of fourth logic cells arranged in a fourth row, wherein each of the fourth logic cells has a third discontinuous active region, and the third discontinuous active regions of two adjacent fourth logic cells are separated from each other by a third isolation structure.