IP Library › Granted Patent US 12,660,351
Granted Patent B2
US 12,660,351 · App. 17/881,862 · Granted Jun 16, 2026

Image sensor comprising deep device isolation pattern

Inventors: Kook Tae Kim (Hwaseong-si, KR); Jingyun Kim (Seogwipo-si, KR); Jonghyeon Noh (Hwaseong-si, KR); Miseon Park (Hwaseong-si, KR); Jaewoong Lee (Yongin-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10F39/807H10F39/011H10F39/199H10F39/811H10F39/8053H10F39/8063
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Quick Facts
Patent No.
US 12,660,351
App. No.
17/881,862
Granted
Jun 16, 2026
Kind
B2
Abstract

An image sensor includes: a substrate including a plurality of pixel regions, a first surface and a second surface opposite to the first surface; and a deep device isolation pattern disposed between adjacent pixel regions of the plurality of pixel regions and penetrating the substrate, wherein the deep deice isolation pattern includes: a semiconductor pattern extended from the second surface toward the first surface; and sidewall insulating patterns interposed between the semiconductor pattern and the substrate, wherein the semiconductor pattern includes sidewall portions and a filling portion, wherein the sidewall portions are provided adjacent to the sidewall insulating patterns, respectively, wherein the filling portion is provided between the sidewall portions, and wherein top surfaces of the sidewall portions are located at a height higher than a top surface of the filling portion,

Claims (23)

1 . An image sensor, comprising

a substrate including a plurality of pixel regions, a first surface and a second surface opposite to the first surface, and

a deep device isolation pattern disposed between adjacent pixel regions of the plurality of pixel regions and penetrating the substrate,

wherein the deep device isolation pattern comprises:

a semiconductor pattern extended from the second surface toward the first surface; and

sidewall insulating patterns interposed between the semiconductor pattern and the substrate,

wherein the semiconductor pattern comprises sidewall portions and a filling portion, wherein the sidewall portions are provided adjacent to the sidewall insulating patterns, respectively, wherein the filling portion is provided between the sidewall portions,

wherein top surfaces of the sidewall portions are located at a height higher than a top surface of the filling portion,

wherein the deep device isolation pattern further comprises a gapfill insulating pattern extending from the first surface of the substrate toward the second surface of the substrate, a portion of the gapfill insulating pattern being disposed between the sidewall portions,

wherein the gapfill insulating pattern includes a first portion disposed between the sidewall portions and a second portion covering the top surfaces of the sidewall portions, and

wherein the first portion and second portion of the gapfill insulating pattern are connected to each other continuously.

2 . The image sensor of claim 1 , wherein each of the sidewall portions and the filling portion comprises a semiconductor material doped to have a conductivity type of p- or n-type.

3 . The image sensor of claim 1 , wherein the deep device isolation pattern further comprises an air gap, wherein the air gap is interposed between the gapfill insulating pattern and the semiconductor pattern.

4 . The image sensor of claim 3 , wherein the air gap is provided to expose a bottom surface of the gapfill insulating pattern.

5 . The image sensor of claim 1 , wherein the deep device isolation pattern further comprises an air gap disposed in the filling portion.

6 . The image sensor of claim 1 , further comprising a shallow device isolation pattern penetrating the substrate from the first surface of the substrate,

wherein the top surfaces of the sidewall portions are located at a height which is higher or lower than a bottom surface of the shallow device isolation pattern.

7 . The image sensor of claim 1 , wherein the top surface of the filling portion has a flat or concave shape.

8 . The image sensor of claim 1 , further comprising a back-side device isolation pattern penetrating the substrate from the second surface of the substrate,

wherein the back-side device isolation pattern is vertically overlapped with the deep device isolation pattern.

9 . The image sensor of claim 1 , wherein the substrate further comprises a center region and an edge region, wherein the center region includes the plurality of pixel regions, and the edge region is adjacent to the center region, and

wherein the image sensor further comprises a contact pattern penetrating the substrate from the second surface of the substrate and is in contact with a bottom surface of the semiconductor pattern in the edge region.

10 . The image sensor of claim 1 , wherein the sidewall insulating patterns are a single layer including silicon oxide or is a multiple layer structure including silicon oxide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2022
From: KIM, KOOK TAE; KIM, JINGYUN; NOH, JONGHYEON; PARK, MISEON; LEE, JAEWOONG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 060731/0358 →
Priority Claims (1)
KR 10-2021-0144278 · Oct 27, 2021 · national
Continuity (1)
Related Publication 20230131769A1 · Apr 27, 2023
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