Chip stack structure and semiconductor package including the same
The inventive concept provides a chip stack structure including a first semiconductor chip and a second semiconductor chip bonded to each other, and a semiconductor package including a plurality of chip stack structures stacked in a vertical direction.
1 . A chip stack structure comprising:
a first semiconductor chip including,
a first semiconductor substrate,
a first semiconductor device layer on the first semiconductor substrate,
a first pad layer including a plurality of first pads arranged in a row in a first direction on the first semiconductor substrate, the plurality of first pads including 1 to M (M is a natural number) first pads, each first pad of the plurality of first pads is configured to receive a corresponding signal of a plurality of signals, each signal of the plurality of signals being different, the plurality of first pads are arranged in a first order from 1 to M in the first direction based on the corresponding signal of the plurality of signals each first pad is configured to receive,
a second pad layer including a plurality of second pads arranged in a row in the first direction on the first pad layer, the plurality of second pads including 1 to M second pads, each second pad of the plurality of second pads is configured to receive a respective signal of the plurality of signals, wherein the plurality of second pads are arranged in a second order from 1 to M in the first direction based on a respective, corresponding signal of the plurality of signals each second pad is configured to receive, the second order being reverse to the first order in the first direction, and
a redistribution layer including a plurality of redistribution patterns located between the first pad layer and the second pad layer, such that the plurality of redistribution patterns to electrically connect a corresponding first pad, among the plurality of first pads, to a corresponding second pad, among the plurality of second pads, such that each corresponding first pad of the plurality of first pads and each corresponding second pad of the plurality of second pads are configured to receive a same signal of the plurality of signals; and
a second semiconductor chip, on the first semiconductor chip, including,
a third pad layer including a plurality of third pads arranged in a row in the first direction on the second pad layer and configured to receive different signals of the plurality of signals, such that each third pad of the plurality of third pads is bonded to a respective second pad, among the plurality of second pads, and
a second semiconductor device layer on the third pad layer.
2 . The chip stack structure of claim 1 , wherein
an N-th pad (N is a natural number less than or equal to M) in the first direction, among the plurality of second pads, is electrically connected to an (M+1−N)-th pad in the first direction, among the plurality of first pads, through the plurality of redistribution patterns.
3 . The chip stack structure of claim 2 , wherein the N-th pad in the first direction, among the plurality of second pads, and the (M+1−N)-th pad in the first direction, among the plurality of first pads, are configured to transmit the same signal.
4 . The chip stack structure of claim 2 , wherein
each signal of the plurality of signals is a different type of signal.
5 . The chip stack structure of claim 1 , wherein,
the plurality of first pads and the plurality of second pads are located at a first distance from a first sidewall of the first semiconductor chip in a second direction perpendicular to the first direction, and
the plurality of third pads are located at the first distance in the second direction from a second sidewall of the second semiconductor chip aligned with the first sidewall of the first semiconductor chip.
6 . The chip stack structure of claim 1 , further comprising:
an external connection pad disposed on the second semiconductor device layer of the second semiconductor chip; and
a passivation layer disposed on the second semiconductor device layer of the second semiconductor chip and having an opening exposing the external connection pad.
7 . The chip stack structure of claim 1 , wherein,
the second pad layer further includes a second pad insulating layer surrounding the plurality of second pads,
the third pad layer further includes a third pad insulating layer surrounding the plurality of third pads, and
the second pad insulating layer is bonded to the third pad insulating layer.
8 . The chip stack structure of claim 7 , wherein the second pad insulating layer and the third pad insulating layer include silicon oxide.
9 . The chip stack structure of claim 1 , wherein the first semiconductor chip and the second semiconductor chip include a NAND flash memory chip.
10 . The chip stack structure of claim 9 , wherein,
the first semiconductor device layer of the first semiconductor chip includes,
a first peripheral circuit structure disposed on the first semiconductor substrate and having a first peripheral circuit, and
a first cell array structure disposed on the first peripheral circuit structure and having a first memory cell array; and
the second semiconductor device layer of the second semiconductor chip includes,
a second cell array structure disposed on the third pad layer and having a second memory cell array, and
a second peripheral circuit structure disposed on the second cell array structure and having a second peripheral circuit.
11 . A semiconductor package comprising:
a package substrate; and
a plurality of chip stack structures stacked in a vertical direction on the package substrate,
wherein each chip stack structure of the plurality of chip stack structures includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip;
wherein the first semiconductor chip includes,
a first semiconductor substrate,
a first semiconductor device layer on the first semiconductor substrate,
a first pad layer including a plurality of first pads arranged in a row in a first direction on the first semiconductor substrate, the plurality of first pads including 1 to M (M is a natural number) first pads, each first pad of the plurality of first pads is configured to receive a corresponding signal of a plurality of signals, each signal of the plurality of signals being different, the plurality of first pads are arranged in a first order from 1 to M in the first direction based on the corresponding signal of the plurality of signals each first pad is configured to receive,
a second pad layer including a plurality of second pads arranged in a row in the first direction on the first pad layer, the plurality of second pads including 1 to M second pads, each second pad of the plurality of second pads is configured to receive a respective signal of the plurality of signals, the plurality of second pads are arranged in a second order from 1 to M in the first direction based on a respective, corresponding signal of the plurality of signals each second pad is configured to receive being reverse to the first order in the first direction, and
a redistribution layer including a plurality of redistribution patterns located between the first pad layer and the second pad layer, such that the plurality of redistribution patterns electrically connect a corresponding first pad, among the plurality of first pads, to a corresponding second pad, among the plurality of second pads, such that each corresponding first pad of the plurality of first pads and each corresponding second pad of the plurality of second pads are configured to transmit a same signal of the plurality of signals; and
wherein the second semiconductor chip includes,
a third pad layer including a plurality of third pads arranged in a row in the first direction on the second pad layer and configured to receive different signals of the plurality of signals, such that each third pad of the plurality of third pads is bonded to a respective second pad, among the plurality of second pads, and
a second semiconductor device layer on the third pad layer.
12 . The semiconductor package of claim 11 , wherein,
in two adjacent chip stack structures, among the plurality of chip stack structures, an upper chip stack structure protrudes laterally from a lower chip stack structure, and
each of the plurality of chip stack structures is configured to electrically connected to the package substrate through a conductive wire.
13 . The semiconductor package of claim 12 , wherein,
each of the plurality of chip stack structures further includes,
an external connection pad disposed on the second semiconductor device layer of the second semiconductor chip, and
a passivation layer disposed on the second semiconductor device layer of the second semiconductor chip and having an opening exposing the external connection pad; and
the conductive wire is connected to the external connection pad.
14 . The semiconductor package of claim 11 , further comprising:
an adhesive material layer located between two adjacent chip stack structures, among the plurality of chip stack structures.
15 . The semiconductor package of claim 11 , further comprising:
a connection bump located between two adjacent chip stack structures, among the plurality of chip stack structures.
16 . The semiconductor package of claim 11 , wherein,
an N-th pad (N is a natural number less than or equal to M) in the first direction, among the plurality of second pads, is electrically connected to an (M+1−N)-th pad in the first direction, among the plurality of first pads, through the plurality of redistribution patterns, and
the N-th pad in the first direction, among the plurality of second pads, is bonded to an N-th pad in the first direction, among the plurality of third pads.
17 . The semiconductor package of claim 11 , wherein, in each of the plurality of chip stack structures,
the first semiconductor chip is bonded to the second semiconductor chip through hybrid bonding, and
the first semiconductor chip and the second semiconductor chip include a NAND flash memory chip.
18 . A chip stack structure comprising:
a first semiconductor chip including,
a first semiconductor substrate,
a first semiconductor device layer on the first semiconductor substrate,
a first pad layer including a plurality of first pads arranged in a row in a first direction on the first semiconductor substrate, the plurality of first pads including 1 to M (M is a natural number) first pads, each first pad of the plurality of first pads is configured to receive a corresponding signal of a plurality of signals, each signal of the plurality of signals being different, the plurality of first pads are arranged in a first order from 1 to M in the first direction based on the corresponding signal of the plurality of signals each first pad is configured to receive and a first pad insulating layer surrounding the plurality of first pads,
a second pad layer including a plurality of second pads arranged in a row in the first direction on the first pad layer, the plurality of second pads including 1 to M second pads, each second pad of the plurality of second pads is configured to receive a respective signal of the plurality of signals, the plurality of second pads are arranged in a second order from 1 to M in the first direction based on a respective, corresponding signal of the plurality of signals each second pad is configured to receive being reverse to the first order in the first direction and a second pad insulating layer surrounding the plurality of second pads, and
a redistribution layer including a plurality of redistribution patterns located between the first pad layer and the second pad layer, wherein the plurality of redistribution patterns electrically connect a corresponding first pad, among the plurality of first pads, to a corresponding second pad, among the plurality of second pads, such that each corresponding first pad of the plurality of first pads and each corresponding second pad of the plurality of second pads are configured to transmit a same signal of the plurality of signals;
a second semiconductor chip, on the first semiconductor chip including,
a third pad layer including a plurality of third pads arranged in a row in the first direction on the second pad layer and configured to receive different signals of the plurality of signals, and a third pad insulating layer surrounding the plurality of third pads, such that each third pad of the plurality of third pads is bonded to a respective second pad, among the plurality of second pads,
a second semiconductor device layer on the third pad layer, and
external connection pads on the second semiconductor chip; and
a passivation layer disposed on the second semiconductor chip and having openings exposing the external connection pads,
wherein,
an N-th pad (N is a natural number less than or equal to M) in the first direction, among the plurality of second pads, is configured to electrically connect to an (M+1−N)-th pad in the first direction, among the plurality of first pads, through the plurality of redistribution patterns, and
the N-th pad in the first direction, among the plurality of second pads, is bonded to an N-th pad in the first direction, among the plurality of third pads.
19 . The chip stack structure of claim 18 , wherein,
the second pad insulating layer is bonded to the third pad insulating layer, and
the second pad insulating layer and the third pad insulating layer include silicon oxide.
20 . The chip stack structure of claim 18 , wherein,
the first semiconductor device layer of the first semiconductor chip includes,
a first peripheral circuit structure disposed on the first semiconductor substrate and having a first peripheral circuit, and
a first cell array structure disposed on the first peripheral circuit structure and having a first memory cell array; and
the second semiconductor device layer of the second semiconductor chip includes,
a second cell array structure disposed on the third pad layer and having a second memory cell array, and
a second peripheral circuit structure disposed on the second cell array structure and having a second peripheral circuit.