Dynamic memory with long retention time
The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a DRAM cell with an access transistor and a storage capacitor, and a word-line coupled to a gate terminal of the access transistor. During the period between the word-line being selected to turn on the access transistor and the word line being unselected to turn off the access transistor, either a first voltage level or a second voltage level is stored in the DRAM cell, wherein the first voltage level is higher than a voltage level of a signal ONE utilized in the DRAM, and the second voltage level is lower than a voltage level of a signal ZERO utilized in the DRAM.
1 . A DRAM chip, comprising:
a first sustaining voltage source outputting a first voltage level which is higher than a voltage level of a signal ONE utilized in the DRAM chip; and
a DRAM cell comprising an access transistor and a storage capacitor;
wherein the first voltage level is stored in the DRAM cell before the access transistor of the DRAM cell is turned off, and a retention time of the DRAM chip is not less than 64 ms at a reference temperature of 85° C.
2 . The DRAM chip in claim 1 , wherein the retention time of the DRAM chip is not less than 64 ms at a reference temperature of 95° C.
3 . The DRAM chip in claim 1 , the retention time of the DRAM chip is not less than 48 ms at a reference temperature of 105° C.
4 . The DRAM chip in claim 1 , and a first sustaining voltage source is supplied from a first sustaining voltage generator external to the DRAM chip.
5 . A DRAM chip, comprising:
a voltage source outputting a first voltage level which is higher than a voltage level of a signal ONE utilized in the DRAM chip; and
a DRAM cell comprising an access transistor and a storage capacitor;
wherein the voltage source is selectively coupled to the DRAM cell before the access transistor of the DRAM cell is turned off, the first voltage level is stored in the DRAM cell before the access transistor of the DRAM cell is turned off, and a retention time of the DRAM chip is not less than 64 ms at a reference temperature of 85° C.
6 . The DRAM chip in claim 5 , wherein the retention time of the DRAM chip is not less than 32 ms at a reference temperature of 95° C.
7 . The DRAM chip in claim 5 , the retention time of the DRAM chip is not less than 32 ms at a reference temperature of 105° C.
8 . A DRAM chip, comprising:
a first sustaining voltage source outputting a first voltage level which is higher than a voltage level of a signal ONE utilized in the DRAM chip; and
a DRAM cell comprising an access transistor and a storage capacitor;
wherein the first voltage level is stored in the DRAM cell before the access transistor of the DRAM cell is turned off, and wherein the first voltage level is dependent on a temperature of the DRAM chip.
9 . The DRAM chip in claim 8 , wherein the temperature of the DRAM chip increase, the first voltage level increases.
10 . The DRAM chip in claim 8 , wherein a retention time of the DRAM chip is not less than 64 ms at a reference temperature of 85° C.
11 . The DRAM chip in claim 8 , wherein the retention time of the DRAM chip is not less than 32 ms at a reference temperature of 95° C.
12 . The DRAM chip in claim 8 , the retention time of the DRAM chip is not less than 16 ms at a reference temperature of 105° C.
13 . A DRAM chip, comprising:
a first group of DRAM cells, each DRAM cell comprising an access transistor and a storage capacitor;
a first group of sense amplifiers electrically coupled to the first group of DRAM cells; and
a first sustaining voltage source outputting a first voltage level which is higher than a voltage level of a signal ONE utilized in the DRAM chip, wherein the first voltage level is stored in the DRAM cell before the access transistor of the DRAM cell is turned off,
wherein a retention time of the DRAM chip is gradually changed from a first reference temperature, a second reference temperature, to a third reference temperature; and
wherein the retention time of the DRAM chip at the first reference temperature, the second reference temperature and the third reference temperature is at least 1.3~2 times a JEDEC defined retention time at the first reference temperature, the second reference temperature and the third reference temperature, respectively.
14 . The DRAM chip in claim 13 , wherein the JEDEC defined retention time at the first reference temperature, the second reference temperature and the third reference temperature is 64 ms, 32 ms, and 16 ms, respectively.
15 . The DRAM chip in claim 13 , wherein the first reference temperature is 85° C., the second reference temperature is 95° C., the third reference temperature is 105° C.
16 . The DRAM chip in claim 13 , wherein
one electrode of the storage capacitor of one DRAM cell is coupled to a predetermined voltage level which is not less than ½ times voltage level of a signal ONE utilized in the DRAM chip.
17 . The DRAM chip in claim 16 , a voltage difference of two electrodes in the storage capacitor is not greater than ½ times voltage level of a signal ONE utilized in the DRAM chip.