HEMT transistor of the normally off type including a trench containing a gate region and forming at least one step, and corresponding manufacturing method
A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
1 . A method for manufacturing normally off heterostructure field-effect transistor (HEMT), the method comprising:
depositing a passivation layer on a semiconductor heterostructure; and
forming, in the passivation layer and the semiconductor heterostructure, a trench including a planar vertical sidewall on a first side of the trench in the semiconductor heterostructure and a plurality of steps laterally opposite the vertical sidewall on a second side of the trench in the semiconductor heterostructure, each step including a respective planar vertical surface and a respective planar horizontal surface, wherein each respective planar horizontal surface is lower than a top surface of the semiconductor heterostructure.
2 . The method of claim 1 , further comprising:
coating the vertical sidewall and the plurality of steps with a dielectric layer; and
depositing a conductive gate region on the dielectric layer in the trench.
3 . The method of claim 2 , further comprising:
coating, after forming the trench in the passivation layer and the semiconductor heterostructure, a top surface of the patterned passivation layer with the dielectric layer; and
depositing the conductive gate region on the dielectric layer on the top surface of the passivation layer.
4 . The method of claim 1 , wherein the heterostructure includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, wherein after forming the trench the vertical sidewall extends entirely through the patterned second semiconductor layer.
5 . The method of claim 4 , wherein the plurality of steps are in the second semiconductor layer.
6 . The method of claim 5 , further comprising, after forming the trench, forming a source metallization extending through the passivation layer and contacting the patterned second semiconductor layer.
7 . The method of claim 4 , further comprising forming the trench entirely through the second semiconductor layer and partially through the first semiconductor layer.
8 . A method for manufacturing normally off heterostructure field-effect transistor (HEMT), the method comprising:
forming a semiconductor heterostructure including:
a first semiconductor layer; and
a second semiconductor layer on the first semiconductor layer;
forming a passivation layer of dielectric material on the semiconductor heterostructure;
forming a trench extending entirely through the passivation layer, entirely through the second semiconductor layer, and partially through the first semiconductor layer, the trench including:
a bottom surface;
a first step on a first side of the trench, the first step having a planar horizontal surface and a planar vertical surface, the planar horizontal surface of the first step being higher in the trench than the bottom surface;
a plurality of second steps on a second side of the trench each having a respective planar horizontal surface and a respective planar vertical surface, the planar horizontal surface of second steps each being higher in the trench than the bottom surface;
forming, after forming the trench, a dielectric layer coating the first and second steps;
forming, after forming the trench, a conductive gate region on the dielectric layer and filling the trench; and
forming, after forming trench, a source metallization extending through the patterned passivation layer and in contact with the patterned second semiconductor layer.
9 . The method of claim 8 , wherein the first and second semiconductor layers include, respectively, gallium nitride and aluminum gallium nitride.
10 . The method of claim 8 , wherein the first and second semiconductor layers are of two materials that are configured to generate a two-dimensional electron gas in the first semiconductor layer.
11 . The method of claim 8 , wherein, after forming the trench and the dielectric layer, the dielectric layer is on a top surface of the patterned passivation layer, wherein after forming the trench, the dielectric layer, and the conductive gate region, the conductive gate region is on the dielectric layer on the top surface of the patterned passivation layer.
12 . The method of claim 8 , wherein the plurality of second steps are in the second semiconductor layer.
13 . The method of claim 8 , wherein the first step is in the first semiconductor layer.
14 . A method for manufacturing normally off heterostructure field-effect transistor (HEMT), the method comprising:
forming a semiconductor heterostructure including:
a first semiconductor layer of gallium nitride; and
a second semiconductor layer of aluminum gallium nitride;
forming a passivation layer of dielectric material on the semiconductor heterostructure;
forming a trench in the passivation layer and the semiconductor heterostructure, the trench including:
a bottom surface;
a planar vertical sidewall in the semiconductor heterostructure on a first side of the trench; and
a plurality of first steps each including a respective planar horizontal surface higher in the trench than the bottom surface and a respective planar vertical surface laterally opposite the planar vertical sidewall on a second side of the trench in the semiconductor heterostructure, wherein the planar vertical sidewall extends entirely through the second semiconductor layer, wherein each respective planar horizontal surface is lower than a top surface of the semiconductor heterostructure.
15 . The method of claim 14 , further comprising:
forming a dielectric layer on the planar vertical sidewall and the plurality of first steps; and
forming a conductive gate region on the dielectric layer in the trench.
16 . The method of claim 15 , wherein after forming the trench and the dielectric layer, the dielectric layer is on a top surface of the patterned passivation layer, wherein after forming the trench, the dielectric layer, and the conductive gate region, the conductive gate region is on the dielectric layer on the top surface of the patterned passivation layer.
17 . The method of claim 14 , wherein the plurality of first steps are in the second semiconductor layer.
18 . The method of claim 14 , wherein the planar vertical sidewall extends partially into the first semiconductor layer.
19 . The method of claim 14 , wherein the first and second semiconductor layers are of two materials that are configured to generate a two-dimensional electron gas in the first semiconductor layer.
20 . The method of claim 14 , further comprising forming, after forming the trench, a source metallization extending through the patterned passivation layer and contacting the patterned second semiconductor layer.