Fine bump pitch die to die tiling incorporating an inverted glass interposer
Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a first layer comprising glass. In an embodiment, conductive pillars are formed through the first layer, and a buildup layer stack is on the first layer. In an embodiment, conductive routing is provided through the buildup layer stack. In an embodiment, a second layer is over a surface of the buildup layer stack opposite from the glass layer.
1 . An electronic package, comprising:
a first layer comprising glass;
conductive pillars through the first layer, wherein the conductive pillars are continuous from a top of the first layer comprising glass to a bottom of the first layer comprising glass, and wherein each of the conductive pillars has an hourglass shaped cross-section with an uppermost surface at a same level as the top of the first layer, and a bottommost surface at a same level as the bottom of the first layer;
a buildup layer stack on the first layer, wherein conductive routing is through the buildup layer stack;
a second layer over a surface of the buildup layer stack opposite from the first layer;
a hybrid bonding layer coupled to a side of the first layer opposite the buildup layer stack, the hybrid bonding layer comprising conductive pads in contact with the conductive pillars, and the hybrid bonding layer comprising a dielectric layer in contact with the glass of the first layer; and
a plurality of solder balls, wherein individual ones of the plurality of solder balls are provided over corresponding ones of the conductive pillars.
2 . The electronic package of claim 1 , wherein the conductive routing comprises at least one via.
3 . The electronic package of claim 2 , wherein the via is a tapered via.
4 . The electronic package of claim 3 , wherein the tapered via has a first end with a first width and a second end with a second width that is smaller than the first width, and wherein a distance between the second end and the first layer is smaller than a distance between the first end and the first layer.
5 . The electronic package of claim 1 , wherein a pitch of the conductive pillars is approximately 25 μm or smaller.
6 . The electronic package of claim 1 , wherein the first layer has a thickness that is approximately 200 μm or smaller.
7 . An electronic package, comprising:
a die, wherein the die comprises:
a second hybrid bonding layer, the second hybrid bonding layer comprising conductive pads and a dielectric layer; and
a package substrate, wherein the package substrate comprises:
a first hybrid bonding layer, comprising:
a third layer comprising glass in contact with the dielectric layer of the second hybrid bonding layer; and
conductive pillars through the third layer, wherein the conductive pillars are continuous from a top of the third layer to a bottom of the third layer, and wherein each of the conductive pillars has an hourglass shaped cross-section with an uppermost surface at a same level as the top of the third layer, and a bottommost surface at a same level as the bottom of the third layer, and wherein the first hybrid bonding layer is coupled to the second hybrid bonding layer, wherein the conductive pillars are in contact with the conductive pads of the second hybrid bonding layer.
8 . The electronic package of claim 7 , wherein the package substrate further comprises:
a buildup layer stack on the third layer, wherein conductive routing is through the buildup layer stack.
9 . The electronic package of claim 8 , wherein the conductive routing includes a via.
10 . The electronic package of claim 9 , wherein the via has a first end with a first width and a second end with a second width that is smaller than the first width, and wherein the second end is closer to the third layer than the first end.
11 . The electronic package of claim 7 , wherein a pitch of the conductive pillars is approximately 25 μm or smaller.
12 . The electronic package of claim 7 , wherein the third layer has a thickness that is approximately 200 μm or smaller.
13 . The electronic package of claim 7 , wherein the first hybrid bonding layer comprises:
conductive pads; and
a dielectric layer around the conductive pads.
14 . The electronic package of claim 13 , wherein the dielectric layer is a silicon oxide.
15 . A method of forming an electronic package, comprising:
forming openings through a glass layer;
attaching the glass layer to a carrier;
filling the openings with a conductive material to form conductive pillars, wherein the conductive pillars are continuous from a top of the glass layer to a bottom of the glass layer, and wherein each of the conductive pillars has an hourglass shaped cross-section with an uppermost surface at a same level as the top of the glass layer, and a bottommost surface at a same level as the bottom of the glass layer;
forming a buildup layer stack with conductive routing over the glass layer;
removing the carrier;
forming a hybrid bonding layer coupled to a side of the glass layer opposite the buildup layer stack, the hybrid bonding layer comprising conductive pads in contact with the conductive pillars, and the hybrid bonding layer comprising a dielectric layer in contact with the glass layer; and
forming a plurality of solder balls, wherein individual ones of the plurality of solder balls are provided over corresponding ones of the conductive pillars.
16 . The method of claim 15 , further comprising:
forming a solder resist layer over the buildup layer stack prior to removing the carrier.
17 . The method of claim 15 , wherein the conductive routing comprises a via with a taper, wherein a first end of the via closest to the glass layer is narrower than a second end of the via.
18 . The method of claim 15 , wherein the glass layer has a thickness of approximately 200 μm or less, and wherein a pitch of the conductive pillars is approximately 25 μm or smaller.
19 . An electronic system, comprising:
a board;
a package substrate coupled to the board, wherein the package substrate comprises a first hybrid bonding layer with a glass layer and conductive pillars, wherein the conductive pillars are continuous from a top of the glass layer to a bottom of the glass layer, and wherein each of the conductive pillars has an hourglass shaped cross-section with an uppermost surface at a same level as the top of the glass layer, and a bottommost surface at a same level as the bottom of the glass layer; and
a die coupled to the package substrate, wherein the die comprises a second hybrid bonding layer, wherein the first hybrid bonding layer is connected to the second hybrid bonding layer, the second hybrid bonding layer comprising conductive pads in contact with the conductive pillars of the first hybrid bonding layer, and the second hybrid bonding layer comprising a dielectric layer in contact with the glass layer of the first hybrid bonding layer.
20 . The electronic system of claim 19 , wherein conductive routing in the package substrate comprises a via with a taper, wherein a first end of the via closest to the glass layer is narrower than a second end of the via.