Three-dimensional semiconductor package with package-on-package semiconductor chips
A semiconductor package includes a first redistribution structure, a first semiconductor package on the first redistribution structure, the first semiconductor package including a first semiconductor chip which includes a first device layer and a first semiconductor substrate including a through electrode, a second semiconductor chip which is on the first semiconductor chip and includes a second device layer and a second semiconductor substrate, and a molding member surrounding the first semiconductor chip, a second redistribution structure on an upper surface of the molding member, and a second semiconductor package on the second redistribution structure, the second semiconductor package including a third semiconductor chip, wherein the second semiconductor chip is apart from the second semiconductor package in a horizontal direction, and an upper surface of the second semiconductor chip is higher than the upper surface of the molding member.
1 . A semiconductor package comprising:
a first redistribution structure;
a first semiconductor package on the first redistribution structure, the first semiconductor package comprising:
a first semiconductor chip which comprises a first device layer and a first semiconductor substrate comprising a through electrode,
a second semiconductor chip which is on the first semiconductor chip and comprises a second device layer and a second semiconductor substrate, and
a molding member surrounding the first semiconductor chip;
a second redistribution structure on an upper surface of the molding member; and
a second semiconductor package on the second redistribution structure, the second semiconductor package comprising a third semiconductor chip; and
an adhesive layer between the first semiconductor chip and the second semiconductor chip to attach the second semiconductor chip on the first semiconductor chip,
wherein the second semiconductor chip is apart from the second semiconductor package in a horizontal direction,
wherein an upper surface of the second semiconductor chip is higher than the upper surface of the molding member,
wherein the upper surface of the molding member is higher than an upper surface of the first semiconductor chip, and
wherein the upper surface of the molding member and an upper surface of the adhesive layer are on a same plane.
2 . The semiconductor package of claim 1 , wherein the upper surface of the second semiconductor chip and an upper surface of the second semiconductor package are at a same vertical level.
3 . The semiconductor package of claim 1 , wherein the first semiconductor package further comprises a first dummy chip on the upper surface of the second semiconductor chip.
4 . The semiconductor package of claim 3 , wherein an upper surface of the first dummy chip and the upper surface of the second semiconductor package are at a same vertical level.
5 . The semiconductor package of claim 4 , wherein the first semiconductor package further comprises a die attach film between the second semiconductor chip and the first dummy chip to attach the first dummy chip on the second semiconductor chip.
6 . The semiconductor package of claim 1 , wherein a horizontal length of the first redistribution structure is greater than a horizontal length of the second redistribution structure.
7 . The semiconductor package of claim 6 , wherein a portion of the first semiconductor chip overlaps the second redistribution structure in a vertical direction.
8 . The semiconductor package of claim 7 , further comprising a conductive pillar apart from the first semiconductor package in the horizontal direction to pass through the molding member in the vertical direction and electrically connect the first redistribution structure with the second redistribution structure.
9 . The semiconductor package of claim 1 , wherein the first device layer of the first semiconductor chip is under the first semiconductor substrate, and
wherein the through electrode has a tapered shape such that a horizontal width of the through electrode decreases progressively as a vertical level increases.
10 . The semiconductor package of claim 1 , wherein the first device layer of the first semiconductor chip is on the first semiconductor substrate, and
wherein the through electrode has a tapered shape such that a horizontal width of the through electrode decreases progressively as a vertical level decreases.
11 . The semiconductor package of claim 1 , wherein the second device layer is under the second semiconductor substrate.
12 . A semiconductor package comprising:
a first redistribution structure;
a first semiconductor package comprising:
a first semiconductor chip which is on the first redistribution structure and comprises a first semiconductor substrate, a through electrode passing through the first semiconductor substrate, and a first device layer on the first semiconductor substrate,
a second semiconductor chip which is on the first semiconductor chip and comprises a second semiconductor substrate and a second device layer on the second semiconductor substrate, and
a molding member surrounding the first semiconductor chip and the second semiconductor chip;
a first dummy chip on an upper surface of the second semiconductor chip;
a second redistribution structure on an upper surface of the molding member and apart from the first dummy chip in a horizontal direction; and
a second semiconductor package on the second redistribution structure, the second semiconductor package comprising a third semiconductor chip,
wherein the first dummy chip is apart from the second semiconductor package in the horizontal direction,
wherein an upper surface of the first dummy chip is higher than the upper surface of the molding member, and
wherein the upper surface of the molding member is higher than an upper surface of the first semiconductor chip.
13 . The semiconductor package of claim 12 , wherein the third semiconductor chip comprises a semiconductor memory chip.
14 . The semiconductor package of claim 12 , wherein the upper surface of the first dummy chip and an upper surface of the second semiconductor package are at a same vertical level.
15 . The semiconductor package of claim 12 , wherein the upper surface of the second semiconductor chip is on a same plane as the upper surface of the molding member.
16 . The semiconductor package of claim 12 , wherein a portion of the first semiconductor chip overlaps the second redistribution structure in a vertical direction.
17 . The semiconductor package of claim 12 , wherein the second semiconductor package comprises a second dummy chip on the third semiconductor chip, and
wherein an upper surface of the second dummy chip is at a same vertical level as the upper surface of the first dummy chip.
18 . A semiconductor package comprising:
a first redistribution structure comprising a first insulation layer and a first redistribution pattern in the first insulation layer;
a first semiconductor package comprising:
a first semiconductor chip which is on the first redistribution structure and comprises a first device layer and a first semiconductor substrate comprising a through electrode,
a second semiconductor chip which is on the first semiconductor chip and comprises a second semiconductor substrate and a second device layer,
an adhesive layer between the first semiconductor chip and the second semiconductor chip,
a molding member surrounding the first semiconductor chip and at least a portion of the second semiconductor chip, and
a conductive pillar passing through the molding member;
a first dummy chip on an upper surface of the second semiconductor chip;
a die attach film between the second semiconductor chip and the first dummy chip to attach the first dummy chip on the second semiconductor chip;
a second redistribution structure on an upper surface of the molding member and apart from the first dummy chip in a horizontal direction; and
a second semiconductor package on the second redistribution structure, the second semiconductor package comprising a third semiconductor chip,
wherein the second device layer is on the second semiconductor substrate,
wherein the first dummy chip is apart from the second semiconductor package in the horizontal direction,
wherein a vertical distance to an upper surface of the first dummy chip from a lower surface of the first redistribution structure is in a range of 1 mm to 1.3 mm,
wherein the upper surface of the first dummy chip and an upper surface of the second semiconductor package are on the same plane, and
wherein an upper surface of the molding member is higher than an upper surface of the first semiconductor chip.