Load latency amelioration using bunch buffers
Techniques for task processing based on load latency amelioration using bunch buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. Sets of control word bits are loaded into buffers. Each buffer is associated with and coupled to a unique compute element within the array of compute elements. The sets of control word bits provide operational control for the compute element with which it is associated. Operations are executed within the array of elements. The operations are based on a selected set of control word bits which comprise a control word bunch.
1 . A processor-implemented method for task processing comprising:
accessing a two-dimensional array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler, wherein the control words that are provided enable parallel execution of tasks, wherein the tasks include two or more tasks that are independent of one another;
loading sets of control word bits into buffers, wherein each buffer is associated with and coupled to a unique compute element within the array of compute elements, and wherein the sets of control word bits provide operational control for the compute element with which it is associated; and
executing operations within the array of compute elements, wherein the operations are based on a selected set of control word bits, wherein the selected set of control word bits comprise a control word bunch.
2 . The method of claim 1 wherein control word bunch enables operational control of a particular compute element for a plurality of cycles.
3 . The method of claim 1 further comprising coupling an iteration counter to each buffer.
4 . The method of claim 3 wherein the iteration counter tracks cycling through the sets of control word bits in the buffer coupled to the iteration counter.
5 . The method of claim 3 further comprising using a pre-stored value in an iteration counter to control operation completion.
6 . The method of claim 3 further comprising generating a task completion signal, based on an iteration counter value.
7 . The method of claim 1 further comprising coupling a pointer register to each buffer.
8 . The method of claim 7 wherein the pointer register indicates a next set of control word bits in a buffer to be executed.
9 . The method of claim 7 wherein the pointer enables operation looping within the compute elements.
10 . The method of claim 9 wherein the operation looping is enabled without additional control word loading.
11 . The method of claim 9 wherein the operation looping accomplishes dataflow processing within statically scheduled compute elements.
12 . The method of claim 1 wherein the stream of wide control words includes two or more data dependent branch operations.
13 . The method of claim 12 wherein the two or more data dependent branch operations require a balanced number of execution cycles.
14 . The method of claim 13 wherein the balanced number of execution cycles is determined by the compiler.
15 . The method of claim 1 further comprising executing a memory operation outside of the array of compute elements.
16 . The method of claim 15 wherein the memory operation is enabled by autonomous compute element operation.
17 . The method of claim 16 wherein the autonomous compute element operation is controlled by one or more sets of control word bits.
18 . The method of claim 1 wherein each buffer enables storing sixteen control word bunches.
19 . The method of claim 1 wherein the buffers comprise operation buffers.
20 . The method of claim 1 wherein the accessing, the providing, the loading, and the executing enable background memory accesses.
21 . The method of claim 20 wherein the background memory accesses reduce load latency.
22 . The method of claim 1 wherein the selected set of control word bits is selected from the stream of control words.
23 . The method of claim 1 wherein the selected set of control word bits is loaded into a bunch buffer.
24 . A computer program product embodied in a non-transitory computer readable medium for task processing, the computer program product comprising code which causes one or more processors to perform operations of:
accessing a two-dimensional array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
providing control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler, wherein the control words that are provided enable parallel execution of tasks, wherein the tasks include two or more tasks that are independent of one another;
loading sets of control word bits into buffers, wherein each buffer is associated with and coupled to a unique compute element within the array of compute elements, and wherein the sets of control word bits provide operational control for the compute element with which it is associated; and
executing operations within the array of compute elements, wherein the operations are based on a selected set of control word bits, wherein the selected set of control word bits comprise a control word bunch.
25 . A computer system for task processing comprising:
a memory which stores instructions;
one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
access a two-dimensional array of compute elements, wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements;
provide control for the array of compute elements on a cycle-by-cycle basis, wherein the control is enabled by a stream of wide control words generated by the compiler, wherein the control words that are provided enable parallel execution of tasks, wherein the tasks include two or more tasks that are independent of one another;
load sets of control word bits into buffers, wherein each buffer is associated with and coupled to a unique compute element within the array of compute elements, and wherein the sets of control word bits provide operational control for the compute element with which it is associated; and
execute operations within the array of compute elements, wherein the operations are based on a selected set of control word bits, wherein the selected set of control word bits comprise a control word bunch.