Stacked FET with local contact
A semiconductor device includes a first source/drain region, a first contact over the first source/drain region, a second source/drain region, and a lateral contact connecting the second source/drain region to a back end of line (BEOL). Portions of the first contact are recessed, and the lateral contact overlaps with the recessed portions of the first contact. The first source/drain region is formed over the second source/drain region.
1 . A semiconductor device, comprising:
a first source/drain region;
a first contact over the first source/drain region, wherein portions of the first contact are recessed;
a second source/drain region;
a lateral contact connecting the second source/drain region to a back end of line (BEOL),
wherein the lateral contact overlaps with the recessed portions of the first contact, and
wherein the first source/drain region is formed over the second source/drain region; and
a second contact comprising:
a first portion over the second source/drain region; and
a second portion connecting the first portion to the lateral contact.
2 . The semiconductor device of claim 1 , wherein the lateral contact is located above the first and second source/drain regions.
3 . The semiconductor device of claim 1 , wherein the first source/drain region is located on a first transistor and the second source/drain region is located on a second transistor, and wherein the first transistor is stacked over the second transistor.
4 . The semiconductor device of claim 1 , further comprising:
a gate contact connecting a gate region to the BEOL; and
a dielectric isolation layer covering the gate contact.
5 . The semiconductor device of claim 4 , wherein a location of the lateral contact is offset from a centerline of the second source/drain region away from the gate region.
6 . The semiconductor device of claim 4 , wherein the gate contact passes through the lateral contact and un-recessed portions of the first contact.
7 . The semiconductor device of claim 6 , wherein the dielectric isolation layer isolates the gate contact from direct contact with the lateral contact and the first contact.
8 . The semiconductor device of claim 5 , wherein a portion of the dielectric isolation layer is connected to the lateral contact.
9 . The semiconductor device of claim 8 , wherein the first contact and the second contact are isolated by an interlayer dielectric (ILD).
10 . A method for forming a semiconductor device, the method comprising:
forming a first source/drain region;
forming a first contact over the first source/drain region, wherein portions of the first contact are recessed;
forming a second source/drain region;
forming a lateral contact connecting the second source/drain region to a back end of line (BEOL),
wherein the lateral contact overlaps with the recessed portions of the first contact, and wherein the first source/drain region is formed over the second source/drain region; and
forming a second contact, wherein the forming the second contact comprises:
forming a first portion over the second source/drain region; and
forming a second portion connecting the first portion to the lateral contact.
11 . The method of claim 10 , wherein the lateral contact is located above the first and second source/drain regions.
12 . The method of claim 10 , wherein the first source/drain region is located on a first transistor and the second source/drain region is located on a second transistor, and wherein the first transistor is stacked over the second transistor.
13 . The method of claim 10 , further comprising:
forming a gate contact connecting a gate region to the BEOL; and
forming a dielectric isolation layer covering the gate contact.
14 . The method of claim 13 , wherein a location of the lateral contact is offset from a centerline of the second source/drain region away from the gate region.
15 . The method of claim 13 , further comprising passing the gate contact through the lateral contact and un-recessed portions of the first contact.
16 . The method of claim 13 , further comprising isolating the gate contact from direct contact with the lateral contact and the first contact by the dielectric isolation layer.
17 . The method of claim 16 , further comprising isolating the first contact and the second contact by an interlayer dielectric (ILD), wherein a portion of the dielectric isolation layer is connected to the lateral contact.
18 . A semiconductor device, comprising:
a source/drain contact connecting a source/drain region to a back end of line (BEOL);
a gate contact connecting a gate region to the BEOL; and
a lateral contact, wherein the gate contact is isolated from direct contact with the lateral contact through a dielectric isolation layer formed over the gate contact.