Semiconductor device structure with liner layer having tapered sidewall and method for preparing the same
A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.
1 . A semiconductor device structure, comprising:
a first dielectric layer disposed over a semiconductor substrate;
a second dielectric layer disposed over the first dielectric layer;
a third dielectric layer disposed over the second dielectric layer;
a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer;
a liner layer surrounding the conductive structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer;
a spacer structure disposed between the liner layer and the second dielectric layer, wherein the spacer structure is in direct contact with a top surface of the first dielectric layer;
an inner silicide portion disposed over the conductive structure;
an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and
an upper plug disposed over the inner silicide portion and the outer silicide portion;
wherein the spacer structure further comprises:
an L-shaped liner; and
a porous low-k dielectric layer enclosed by the L-shaped liner and the liner layer.
2 . The semiconductor device structure of claim 1 , wherein the liner layer is in direct contact with the spacer structure, the conductive structure, and the outer silicide portion.
3 . The semiconductor device structure of claim 1 , wherein a bottom surface of the liner layer is higher than a bottom surface of the first dielectric layer, and an angle between the tapered sidewall and the bottom surface of the liner layer is greater than 90 degrees.
4 . The semiconductor device structure of claim 1 , wherein the conductive structure further comprises:
a metal filling portion;
a metal layer surrounding the metal filling portion; and
a barrier layer surrounding the metal layer.
5 . The semiconductor device structure of claim 4 , wherein a top width of the metal filling portion is greater than a bottom width of the metal filling portion.
6 . The semiconductor device structure of claim 4 , wherein the metal filling portion comprises copper (Cu), and the metal layer comprises copper-manganese (Cu—Mn) alloy.