Damascene interconnect structures with low resistance vias for integrated circuits
Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.
1 . A integrated circuit (IC) interconnect structure, comprising:
a first line metallization;
a via metallization comprising a fill metal in direct physical contact with the first line metallization over an area including a center of a bottom of the via metallization, and comprising a barrier material in direct physical contact with a sidewall of the fill metal and encircling the area including the center of the bottom of the via metallization; and
a second line metallization over, and coupled to, the first line metallization through the via metallization, wherein the barrier material is at a bottom of the second line metallization, and the second line metallization comprises the fill metal in direct physical contact with the barrier material at the bottom of the second line metallization.
2 . The IC interconnect structure of claim 1 , wherein the barrier material comprises at least one of graphene or a metal chalcogenide.
3 . The IC interconnect structure of claim 1 , wherein the barrier material within an upper portion of the via metallization has a lateral width of less than 1.5 nm adjacent to the sidewall of the fill metal.
4 . The IC interconnect structure of claim 1 , wherein:
a foot of the barrier material is in direct physical contact with the first line metallization over a second area at the bottom of the via metallization, wherein the second area encloses the area including the center of the bottom of the via metallization.
5 . The IC interconnect structure of claim 4 , wherein the foot of barrier material has a lateral width of at least 2 nm, and wherein the barrier material within an upper portion of the via metallization has a lateral width of less than 1.5 nm adjacent to the sidewall of the fill metal.
6 . The IC interconnect structure of claim 4 , wherein the foot of barrier material has a thickness between the fill metal and the first line metallization substantially equal to a thickness of the barrier material at the bottom of the second line metallization.
7 . The IC interconnect structure of claim 1 , further comprising one or more interlayer dielectric (ILD) materials, wherein the via metallization is within a first thickness of the ILD materials and the second line metallization is within a second thickness of the ILD materials, and wherein the barrier material is between the ILD materials and the fill metal, and wherein the barrier material has a higher relative permittivity than the ILD materials.
8 . The IC interconnect structure of claim 1 , wherein the first line metallization comprises copper and the fill metal comprises copper.
9 . An integrated circuit (IC) structure, comprising:
a device layer comprising a plurality of transistors comprising one or more semiconductor materials; and
a plurality of interconnect levels, the interconnect levels further comprising:
a first line metallization coupled to a terminal of one or more of the transistors;
a via metallization comprising a fill metal in direct physical contact with the first line metallization over an area including a center of a bottom of the via metallization, and comprising a 2D barrier material in direct physical contact with a sidewall of the fill metal and encircling the area at the center of the bottom of the via metallization, wherein the 2D barrier material comprises a metal chalcogenide or graphene; and
a second line metallization over, and coupled to the first line metallization through the via metallization, wherein the 2D barrier material is at a bottom of the second line metallization, and the second line metallization comprises the fill metal in direct physical contact with the 2D barrier material at the bottom of the second line metallization.
10 . A computer platform comprising:
a power supply; and
the IC structure of claim 9 coupled to the power supply.
11 . The IC structure of claim 9 , wherein the first line metallization comprises copper and the fill metal comprises copper.
12 . The IC structure of claim 11 , wherein the barrier material within an upper portion of the via metallization has a lateral width of less than 1.5 nm adjacent to the sidewall of the fill metal.
13 . The IC structure of claim 12 , wherein:
the fill metal is in direct physical contact with the first line metallization over the area including the center of the bottom of the via metallization; and
a foot of the barrier material is in direct physical contact with the first line metallization over a second area at the bottom of the via metallization, wherein the second area encloses the area including the center of the bottom of the via metallization, and the foot of barrier material has a lateral width of at least 2 nm.
14 . The IC structure of claim 13 , wherein the foot of barrier material has a thickness between the fill metal and the first line metallization that is substantially equal to a thickness of the barrier material at the bottom of the second line metallization.