Power semiconductor module and manufacturing method
In one embodiment, a power semiconductor module includes a main substrate, semiconductor chips mounted on the main substrate, and an auxiliary substrate also mounted on the main substrate. The power semiconductor module is capable of handling a current of 10 A or more. The auxiliary substrate is a printed circuit board having at least one carrier layer that is based on an organic material. The auxiliary substrate provides a common contact platform for at least some of the first semiconductor chips. The auxiliary substrate is attached to the main substrate by a joining layer located at a bottom side of the at least one auxiliary substrate facing the main substrate. The joining layer is a continuous organic adhesive layer of an adhesive foil or a double-faced adhesive tape.
1 . A power semiconductor module comprising:
a main substrate;
a plurality of first semiconductor chips mounted on the main substrate;
a first auxiliary substrate mounted on the main substrate, the first auxiliary substrate comprising a top face remote from the main substrate; and
a second auxiliary substrate mounted on the main substrate, the second auxiliary substrate comprising a top face remote from the main substrate;
wherein the power semiconductor module is capable of handling a current of 10 A or more;
wherein the first auxiliary substrate is a printed circuit board comprising at least one carrier layer that is based on an organic material;
wherein the first auxiliary substrate provides a common contact platform for first ones of the first semiconductor chips;
wherein the second auxiliary substrate provides a common contact platform for second ones of the first semiconductor chips; and
wherein the first auxiliary substrate is attached to the main substrate by a joining layer located at a bottom side of the first auxiliary substrate facing the main substrate, the joining layer comprising a continuous organic adhesive layer, wherein the joining layer is an adhesive foil or a double-faced adhesive tape;
wherein the first auxiliary substrate is a multi-layer substrate; and
wherein the first auxiliary substrate comprises an interior conductive layer that is configured as an electrical shielding layer to reduce electromagnetic coupling.
2 . The power semiconductor module according to claim 1 , wherein the organic material comprises a fiber reinforced organic material selected from the group consisting of polytetrafluoroethylene (PTFE), FR-2 (phenolic cotton paper), FR-3 (cotton paper and epoxy), FR-4 (woven glass and epoxy), FR-5 (woven glass and epoxy), FR-6 (matte glass and polyester), G-10 (woven glass and epoxy), CEM-1 (cotton paper and epoxy), CEM-2 (cotton paper and epoxy), CEM-3 (non-woven glass and epoxy), CEM-4 (woven glass and epoxy), and CEM-5 (woven glass and polyester).
3 . The power semiconductor module according to claim 1 , wherein each common contact platform is a gate contact for the respective first semiconductor chips.
4 . The power semiconductor module according to claim 1 , wherein the top face of the first auxiliary substrate comprises a metal layer so that there is a direct electrical connection between the metal layer and the main substrate, and wherein the first ones of the first semiconductor chips are electrically directly contacted to the metal layer, wherein the first ones of the first semiconductor chips are electrically connected in parallel.
5 . The power semiconductor module according to claim 1 , further comprising second semiconductor chips mounted on the main substrate, wherein the second semiconductor chips are electrically separated from the first auxiliary substrate and the second auxiliary substrate.
6 . The power semiconductor module according to claim 1 , wherein the first semiconductor chips comprise chips selected from the group consisting of MOSFETs, MISFETs, IGBTs, BJTs, thyristors, GTOs, GCTs, and JFETs.
7 . The power semiconductor module according to claim 1 , wherein the main substrate is a direct bonded copper substrate comprising a central ceramic layer and at least one metallization on each main side of the ceramic layer.
8 . The power semiconductor module according to claim 1 , wherein the first ones of the first semiconductor chips comprise at least three first semiconductor chips for which the first auxiliary substrate provides the common contact platform;
wherein the top face of the first auxiliary substrate comprises conductor tracks, each one of the conductor tracks is assigned to up to two of the first ones of the first semiconductor chips; and
wherein the conductor tracks have different lengths so that otherwise existing length differences of electrical connection lines in the power semiconductor module to the first ones of the first semiconductor chips running over the first auxiliary substrate are compensated for.
9 . The power semiconductor module according to claim 1 ,
wherein conductor tracks of the first auxiliary substrate run electrically in parallel or anti-parallel in sections; and
wherein, seen in top view of the top face, the first ones of the first semiconductor chips are arranged along two sides of the first auxiliary substrate, so that the first auxiliary substrate is located between the first ones of the first semiconductor chips.
10 . A power semiconductor module comprising:
a main substrate;
an auxiliary substrate mounted on the main substrate, wherein the auxiliary substrate is a printed circuit board comprising a carrier layer based on an organic material and wherein the auxiliary substrate comprises a plurality of resistors;
a joining layer located at a bottom side of the auxiliary substrate to attach the auxiliary substrate to the main substrate, the joining layer comprising a continuous organic adhesive layer, wherein the joining layer is an adhesive foil or a double-faced adhesive tape;
a plurality of first power semiconductor chips mounted directly on the main substrate and electrically connected to the auxiliary substrate, each of the resistors being assigned to up to two of the first semiconductor chips, wherein the power semiconductor module is capable of handling a current of 10 A or more;
wherein the plurality of first semiconductor chips comprises at least three first semiconductor chips for which the auxiliary substrate provides a common contact platform;
wherein a top face of the auxiliary substrate comprises conductor tracks, each one of the conductor tracks is assigned to up to two of the first semiconductor chips; and
wherein the conductor tracks have different lengths.
11 . The power semiconductor module according to claim 1 , wherein the first auxiliary substrate comprises a plurality of resistors, each of the resistors being assigned to up to two of the first ones of the first semiconductor chips.
12 . The power semiconductor module according to claim 11 , wherein the resistors comprise discrete devices mounted on the top face of the first auxiliary substrate.
13 . The power semiconductor module according to claim 11 , wherein the resistors are structures formed in the top face or in an interior of the first auxiliary substrate.
14 . The power semiconductor module according to claim 1 , wherein the first auxiliary substrate is provided with at least two different types of electric devices or semiconductor chips.
15 . The power semiconductor module of claim 10 , further comprising a plurality of second power semiconductor chips mounted on the main substrate, the second power semiconductor chips not being electrically connected to the auxiliary substrate.
16 . The power semiconductor module according to claim 15 , further comprising a second auxiliary substrate that provides a common contact platform for the second power semiconductor chips, the common contact platform being a gate contact.
17 . A method for manufacturing a power semiconductor module, the method comprising:
providing a main substrate;
mounting an auxiliary substrate onto the main substrate, the auxiliary substrate comprising a printed circuit board having a carrier layer that is based on an organic material, the auxiliary substrate being mounted using a joining layer located at a bottom side of the auxiliary substrate facing the main substrate to attach the auxiliary substrate to the main substrate, the joining layer comprising a continuous organic adhesive layer, wherein the joining layer is an adhesive foil or a double-faced adhesive tape; and
mounting a plurality of first semiconductor chips over the main substrate, wherein the auxiliary substrate provides a common contact platform for at least some of the first semiconductor chips;
wherein the power semiconductor module is capable of handling a current of 10 A or more; and
wherein the auxiliary substrate comprises a pre-applied primary material layer that forms the joining layer, wherein prior to mounting the auxiliary substrate the main substrate is free of any primary material layer or joining layer configured for mounting the auxiliary substrate.
18 . The method according to claim 17 , wherein the primary material layer is the adhesive foil so that the primary material layer is a solid component or the double-faced adhesive tape, which comprises a peel-off coating before mounting.