Apparatus and methods for managing selector device threshold voltage drift
An apparatus is provided that includes a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistance-switching memory element coupled in series with a selector element that has a threshold voltage. The control circuit is configured to use a first pulse having a first polarity to first access the memory cell, use a second pulse having a second polarity opposite the first polarity to second access the memory cell, and use a third pulse having the first polarity to third access the memory cell. The third pulse is configured to reduce a rate of threshold voltage drift of the selector element.
1 . An apparatus comprising:
a memory cell comprising a reversible resistance-switching memory element coupled in series with a selector element that comprises a threshold voltage; and
a control circuit coupled to the memory cell, the control circuit configured to perform a self-referenced read operation by:
use a first pulse comprising a first polarity to first access the memory cell;
use a second pulse comprising a second polarity opposite the first polarity to second access the memory cell; and
use a third pulse comprising the first polarity to third access the memory cell,
wherein the third pulse is configured to reduce a rate of threshold voltage drift of the selector element.
2 . The apparatus of claim 1 , wherein the reversible resistance-switching memory element comprises a magnetic memory element.
3 . The apparatus of claim 1 , wherein the reversible resistance-switching memory element comprises a magnetic tunnel junction.
4 . The apparatus of claim 1 , wherein the selector element comprises a threshold selector device.
5 . The apparatus of claim 1 , wherein the selector element comprises an ovonic threshold switch.
6 . The apparatus of claim 1 , wherein the selector element comprises a threshold voltage that drifts at an increasing rate with time.
7 . The apparatus of claim 1 , wherein the selector element may be selectively turned ON.
8 . The apparatus of claim 1 , wherein the first pulse, the second pulse and the third pulse each turn ON the selector element.
9 . The apparatus of claim 1 , wherein the control circuit is further configured to perform a first read and a second read of the reversible resistance-switching memory element prior to the second pulse.
10 . The apparatus of claim 1 , wherein the control circuit is further configured to perform a destructive read of the reversible resistance-switching memory element prior to the second pulse.
11 . The apparatus of claim 1 , wherein the first pulse comprises a RESET pulse and the second pulse comprises a SET pulse.
12 . The apparatus of claim 1 , wherein the third pulse is configured to turn ON the selector element without disturbing a data state of the reversible resistance-switching memory element.
13 . The apparatus of claim 1 , wherein the control circuit is further configured to use the third pulse to third access the memory cell less than about 100 nsec after using the second pulse to second access the memory cell.
14 . An apparatus comprising:
a cross-point memory array comprising a plurality of memory cells, each memory cell comprising a magnetic tunnel junction memory element coupled in series with a selector element;
a control circuit coupled to the cross-point memory array, the control circuit configured to:
perform a self-referenced read operation of each of the plurality of memory cells; and
for each memory cell that changed from a first direction of magnetization to a second direction of magnetization as a result of the self-referenced read operation:
apply a SET pulse to change direction of magnetization from the second direction of magnetization to the first direction of magnetization; and
apply a post-set pulse comprising a polarity opposite the polarity of the SET pulse.
15 . The apparatus of claim 14 , wherein each selector element comprises a threshold selector device.
16 . The apparatus of claim 14 , wherein each selector element comprises an ovonic threshold switch.
17 . The apparatus of claim 14 , wherein each selector element comprises a threshold voltage that drifts at an increasing rate with time.
18 . The apparatus of claim 14 , wherein the post-set pulse is configured to reduce a bit error rate of the plurality of memory cells.
19 . A method comprising:
determining a bit error rate of a plurality of memory cells, each comprising an ovonic threshold switch coupled in series with a magnetic memory element, by:
performing a sequence of self-referenced read operations of each of the memory cells, each self-referenced read operation comprising a RESET pulse comprising a first polarity; and
after every other self-referenced read operation, applying to the memory cells a SET pulse comprising a second polarity, and a post-set pulse comprising the first polarity,
wherein the post-set pulses are configured to reduce the bit error rate of the plurality of memory cells.
20 . The method of claim 19 , wherein the magnetic memory elements each comprise a magnetic tunnel junction.