Heterostructure and method of fabrication
The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.
1 . A surface acoustic wave device, comprising:
a high-resistivity silicon support substrate;
a piezoelectric material bonded over a top surface of the high-resistivity silicon support substrate; and
a charge trapping layer comprising poly-crystalline silicon disposed on the high-resistivity silicon support substrate.
2 . The surface acoustic wave device of claim 1 , wherein a resistivity of the high-resistivity silicon support substrate is higher than 1 kOhm/cm.
3 . The surface acoustic wave device of claim 2 , wherein the resistivity of the high-resistivity silicon support substrate is higher than 5 kOhm/cm.
4 . The surface acoustic wave device of claim 1 , wherein at least one microelectronic device is present on or in the piezoelectric material.
5 . The surface acoustic wave device of claim 4 , wherein the at least one microelectronic device comprises a CMOS device.
6 . The surface acoustic wave device of claim 1 , wherein the charge trapping layer comprises porous silicon.
7 . The surface acoustic wave device of claim 1 , wherein the piezoelectric material comprises at least one recess extending into the piezoelectric material from an interface between the high-resistivity silicon support substrate and the piezoelectric material.
8 . The surface acoustic wave device of claim 7 , wherein the at least one recess forms a trench extending over an entire width of a wafer.
9 . The surface acoustic wave device of claim 8 , wherein the at least one recess extends from the interface between the high-resistivity silicon support substrate and the piezoelectric material entirely through the piezoelectric material to an opposing free surface of the piezoelectric material.
10 . The surface acoustic wave device of claim 9 , wherein a plurality of the at least one recesses separate the piezoelectric material into singular piezoelectric islands.
11 . The surface acoustic wave device of claim 9 , wherein the charge trapping layer has a thickness less than 10 μm.
12 . The surface acoustic wave device of claim 9 , wherein the piezoelectric material is bonded over the top surface of the high-resistivity silicon support substrate through an adhesive layer.
13 . A method of forming a surface acoustic wave device, the method comprising:
providing a high-resistivity silicon support substrate;
disposing a functional layer as a poly-crystalline silicon layer on the high-resistivity silicon support substrate to form a charge trapping layer; and
bonding a piezoelectric material over a top surface of the high-resistivity silicon support substrate.
14 . The method of claim 13 , wherein bonding the piezoelectric material over the top surface of the high-resistivity silicon support substrate comprises bonding the piezoelectric material over a top surface of the functional layer.
15 . The method of claim 13 , wherein bonding the piezoelectric material over the top surface of the high-resistivity silicon support substrate comprises bonding the piezoelectric material over the top surface of the high-resistivity silicon support substrate with an adhesive layer.
16 . The method of claim 13 , further comprising forming the charge trapping layer by introducing a predetermined level of porosity.
17 . The method of claim 13 , further comprising disposing at least one microelectronic device on or in the piezoelectric material.
18 . The method of claim 17 , wherein disposing the at least one microelectronic device on or in the piezoelectric material, comprises disposing a CMOS device on or in the piezoelectric material.