Stress-reduction structures for a compound semiconductor layer stack
Structures including a compound semiconductor layer stack and methods of forming such structures. The structure comprises a device region on a substrate. The device region includes a first section of a layer stack that has a plurality of semiconductor layers, and each semiconductor layer comprises a compound semiconductor material. The structure further comprises an isolation structure disposed about the section of the layer stack, and a device in the device region. The isolation structure penetrates through the layer stack to the substrate.
1 . A structure comprising:
a substrate;
an interconnect structure on the substrate;
a device region on the substrate, the device region including a section of a layer stack that includes a plurality of compound semiconductor layers, and the layer stack having a top surface;
an isolation structure surrounding the section of the layer stack, the isolation structure including a plurality of recesses penetrating from the top surface of the layer stack fully through the layer stack to the substrate, the isolation structure including a first layer that has a first portion as a liner inside each of the plurality of recesses and a second portion on the top surface of the section of the layer stack, the isolation structure including a second layer inside each of the plurality of recesses on the first portion of the first layer, the first layer comprising silicon nitride, and the second layer comprising a dielectric material; and
a high-mobility field-effect transistor in the device region,
wherein the second layer is conformal with a thickness that is uniform independent of topography, and the second layer only partially fills the plurality of recesses.
2 . The structure of claim 1 wherein the high-mobility field-effect transistor includes a source ohmic contact, a drain ohmic contact, and a gate.
3 . The structure of claim 1 wherein the isolation structure includes a first portion having a first aspect ratio and a second portion having a second aspect ratio different from the first aspect ratio, and the first portion of the isolation structure and the second portion of the isolation structure adjoin different portions of the device region.
4 . The structure of claim 3 wherein the first portion and the second portion of the isolation structure have equal heights.
5 . A structure comprising:
a substrate;
an interconnect structure on the substrate;
a device region on the substrate, the device region including a section of a layer stack that includes a plurality of compound semiconductor layers, and the layer stack having a top surface;
an isolation structure surrounding the section of the layer stack, the isolation structure including a plurality of recesses penetrating from the top surface of the layer stack fully through the layer stack to the substrate, the isolation structure including a first layer that has a first portion as a liner inside each of the plurality of recesses and a second portion on the top surface of the section of the layer stack, the isolation structure including a second layer inside each of the plurality of recesses on the first portion of the first layer, the first layer comprising silicon nitride, and the second layer comprising a polycrystalline semiconductor material; and
a high-mobility field-effect transistor in the device region.
6 . A structure comprising:
a substrate;
an interconnect structure on the substrate;
a device region on the substrate, the device region including a section of a layer stack that includes a plurality of compound semiconductor layers, and the layer stack having a top surface;
an isolation structure surrounding the section of the layer stack, the isolation structure including a plurality of recesses penetrating from the top surface of the layer stack fully through the layer stack to the substrate, the isolation structure including a first layer that has a first portion as a liner inside each of the plurality of recesses and a second portion on the top surface of the section of the layer stack, the isolation structure including a second layer inside each of the plurality of recesses on the first portion of the first layer, the first layer comprising silicon nitride, and the second layer comprising a metal; and
a high-mobility field-effect transistor in the device region.
7 . The structure of claim 1 wherein at least one of the plurality of compound semiconductor layers comprises gallium nitride.
8 . The structure of claim 1 wherein the device region is fully surrounded by the plurality of recesses in a patterned area, and the plurality of recesses occupy 40 percent to 90 percent of the patterned area.
9 . The structure of claim 1 wherein the plurality of recesses have respective bottoms that adjoin the substrate, and further comprising:
a damaged region of semiconductor material in the substrate adjacent to the respective bottoms of the plurality of recesses.
10 . The structure of claim 1 wherein the plurality of recesses have respective bottoms that adjoin the section of the layer stack, and further comprising:
a damaged region of semiconductor material in the section of the layer stack adjacent to a sidewall of each of the plurality of recesses.
11 . The structure of claim 1 further comprising:
a passive device in the interconnect structure,
wherein the isolation structure is disposed between the passive device and the substrate, the passive device overlaps with the isolation structure, and the passive device does not overlap with a portion of the layer stack.
12 . The structure of claim 1 wherein the second layer has a top surface that is coplanar with the second portion of the first layer.
13 . The structure of claim 1 wherein the dielectric material is silicon dioxide.
14 . The structure of claim 5 wherein the second layer has a top surface that is coplanar with the second portion of the first layer.
15 . The structure of claim 6 wherein the second layer has a top surface that is coplanar with the second portion of the first layer.
16 . The structure of claim 1 wherein the substrate comprises a single-crystal semiconductor material, and the plurality of recesses extend through an entire thickness of the layer stack to the single-crystal semiconductor material of the substrate.
17 . The structure of claim 5 wherein the isolation structure includes a first portion having a first aspect ratio and a second portion having a second aspect ratio different from the first aspect ratio, and the first portion of the isolation structure and the second portion of the isolation structure adjoin different portions of the device region.
18 . The structure of claim 5 wherein the substrate comprises a single-crystal semiconductor material, and the plurality of recesses extend through an entire thickness of the layer stack to the single-crystal semiconductor material of the substrate.
19 . The structure of claim 6 wherein the isolation structure includes a first portion having a first aspect ratio and a second portion having a second aspect ratio different from the first aspect ratio, and the first portion of the isolation structure and the second portion of the isolation structure adjoin different portions of the device region.
20 . The structure of claim 6 wherein the substrate comprises a single-crystal semiconductor material, and the plurality of recesses extend through an entire thickness of the layer stack to the single-crystal semiconductor material of the substrate.