Three-dimensional non-volatile SRAM incorporating thin-film device layer
A shadow RAM or “non-volatile SRAM” memory cell is implemented in a much smaller area by building the cell upward rather than outward. By stacking non-volatile storage devices above or below an SRAM cell, a smaller cell can be provided and result in a lower cost memory device. In certain embodiments, such a memory cell includes a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes, and a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes.
1. A memory cell comprising:
a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes; and
a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes;
wherein the non-volatile storage devices comprise modifiable conductance switch devices, each disposed within a respective NAND string.
2. The memory cell as recited in claim 1 wherein the non-volatile storage devices comprise a charge storage dielectric.
3. The memory cell as recited in claim 1 wherein the non-volatile storage devices comprise a floating gate.
4. The memory cell as recited in claim 1 further comprising:
a pair of word line access devices disposed on the first device layer and respectively coupling the pair of cross-coupled internal nodes to a pair of bit lines; and
a pair of load devices formed on the second device layer, said pair of load devices respectively coupled to the pair of cross-coupled internal nodes.
5. The memory cell as recited in claim 4 wherein:
said pair of load devices comprise semiconductor thin film resistors; and
said pair of non-volatile devices comprises thin film devices having a charge storage dielectric and each arranged within a respective NAND string.
6. The memory cell as recited in claim 5 wherein:
each NAND string includes one of said pair of non-volatile devices disposed between a respective group of one or more select devices at each end of said NAND string.
7. The memory cell as recited in claim 6 wherein:
at least one of said groups of one or more select devices numbers at least two such devices in senes.
8. An integrated circuit including a memory array of memory cells, each memory cell as recited in claim 1 .
9. A computer readable medium encoding a memory cell as recited in claim 1 .
10. A memory cell comprising:
a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes;
a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes; and
a second pair of non-volatile storage devices disposed on a device layer other than the first device layer and coupled to the cross-coupled nodes.
11. The memory cell as recited in claim 10 wherein:
the second pair of non-volatile storage devices are disposed on a device layer other than the second device layer.
12. The memory cell as recited in claim 11 wherein:
the second pair of non-volatile storage devices are disposed on a third device layer;
the memory cell further comprises a first pair of NAND strings on the second device layer, each including a respective non-volatile storage device from the first pair of such devices; and
the memory cell further comprises a second pair of NAND strings on the third device layer, each including a respective non-volatile storage device from the second pair of such devices.
13. The memory cell as recited in claim 10 wherein:
the second pair of non-volatile storage devices are disposed on the second device layer; and
the memory cell further comprises a pair of NAND strings, each including a respective non-volatile storage device from each of the first and second pair of such devices.
14. An integrated circuit including a memory array of memory cells, each memory cell as recited in claim 10 .
15. A computer readable medium encoding a memory cell as recited in claim 10 .
16. A memory cell comprising:
a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes:
a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes: and
a pair of word line access devices disposed on a third device layer, said pair of word line access devices respectively coupling the pair of cross-coupled internal nodes to a pair of bit lines.
17. The memory cell as recited in claim 16 further comprising:
a pair of load devices formed on a fourth device layer, said pair of load devices respectively coupled to the pair of cross-coupled internal nodes.
18. The memory cell as recited in claim 17 further comprising:
a pair of zias forming a portion of the cross-coupled nodes and respectively coupling together the pair of load devices, the pair of non-volatile devices, the pair of word line access devices, and the pair of cross-coupled devices.
19. The memory cell as recited in claim 17 wherein:
the first device layer comprises a semiconductor substrate layer;
the pair of non-volatile storage device comprises a pair of TFT devices having a charge storage dielectric and arranged within a respective NAND string; and
the pair of load devices comprise semiconductor thin film resistors.
20. An integrated circuit including a memory array of memory cells, each memory cell as recited in claim 16 .
21. A computer readable medium encoding a memory cell as recited in claim 16 .
22. A memory cell comprising:
a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes;
a pair of non-volatile storage devices disposed on a second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes; and
a pair of load devices formed on a device layer other than the first device layer, said pair of load devices respectively coupled to the pair of cross-coupled internal nodes.
23. The memory cell as recited in claim 22 wherein the non-volatile storage devices comprise modifiable conductance switch devices, each disposed within a respective NAND string.
24. The memory cell as recited in claim 22 wherein the non-volatile storage devices comprise one-time-programmable devices.
25. The memory cell as recited in claim 22 wherein the non-volatile storage devices comprise antifuse devices.
26. The memory cell as recited in claim 22 wherein:
the pair of load devices comprise semiconductor thin film resistors.
27. The memory cell as recited in claim 22 wherein:
the pair of load devices comprise a second pair of cross-coupled transistors which are complementary to the first pair of cross-coupled transistors.
28. The memory cell as recited in claim 22 wherein the pair of non-volatile storage device comprises a pair of passive element memory cell devices.
29. An integrated circuit including a memory array of memory cells, each memory cell as recited in claim 22 .
30. A computer readable medium encoding a memory cell as recited in claim 22 .
31. A method for operating a memory comprising:
writing data to a memory cell, said memory cell comprising a pair of cross-coupled devices disposed on a first device layer and defining a pair of internal cross-coupled nodes;
storing data written into the memory cell into a pair of non-volatile storage devices disposed on second device layer above or below the pair of cross-coupled devices and coupled to the cross-coupled nodes;
recalling data from the pair of non-volatile storage devices into the memory cell; and
reading the memory cell while decoupling the pair of non-volatile storage devices from the memory cell.
32. A shadow RAM memory cell comprising:
an SRAM memory cell including at least a pair of cross-coupled transistors disposed on a first device layer and defining a pair of internal cross-coupled nodes, and further including a pair of access transistors; and
non-volatile storage means disposed at least partially on a second device layer above or below the pair of cross-coupled devices, and coupled to the cross-coupled internal nodes for storing at least two separate bits of information, either of which may be recalled into the SRAM memory cell.