Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof
View Patent ↗The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the <100> direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
1. A complementary metal oxide semiconductor (CMOS) structure comprising:
a rotated Si-containing semiconductor substrate having a (100) crystal orientation and a wafer notch along a <100> direction;
at least one pFET located on a surface of said rotated Si-containing semiconductor substrate, said at least one pFET having a channel that is along said <100> direction; and
at least one stressed material located at least within, or on, a surface of said rotated Si-containing semiconductor substrate that induces a stress on said channel of each pFET, wherein said at least one stressed material is a stressed wall that includes a compressively strained material.
2. The CMOS structure of claim 1 wherein said rotated Si-containing semiconductor substrate comprises a Si-containing semiconductor material selected from the group consisting of Si, SiGe, SiC, SiGeC, silicon-on-insulators, silicon germanium-on insulators and combinations thereof.
3. The CMOS structure of claim 1 wherein said rotated Si-containing semiconductor substrate is strained, unstrained or a combination of strained and unstrained layers.
4. The CMOS structure of claim 1 further comprising at least one isolation region located within said rotated Si-containing semiconductor substrate.
5. The CMOS structure of claim 1 wherein said at least one pFET comprises a gate dielectric, a gate conductor, at least one sidewall spacer, source/drain extensions and source/drain regions.
6. The CMOS structure of claim 1 wherein said stressed liner comprises a nitride, a high density plasma oxide, or combinations thereof.
7. The CMOS structure of claim 1 wherein said embedded stressed well comprises Si or Si containing at least one of C or Ge.
8. The CMOS structure of claim 7 wherein said embedded stressed well comprises SiGe.
9. The CMOS structure of claim 1 wherein said stressed well includes source and drain diffusion regions and source and drain extension regions.
10. The CMOS structure of claim 1 further comprising at least one nFET located adjacent to said at least one pFET.
11. The CMOS structure of claim 10 wherein said at least one nFET is under stress, said stress is caused by said at least one stressed material.
12. The CMOS structure of claim 11 wherein said stressed material further includes a stressed liner.
13. The CMOS structure of claim 11 wherein said stressed material includes an embedded stressed well comprising Si or Si containing at least one of C or Ge.
14. The CMOS structure of claim 10 wherein said stressed material comprises a combination of a stressed liner and said embedded stressed well.
15. The CMOS structure of claim 14 wherein said stressed liner comprises a compressive nitride and said embedded stressed well comprises SiGe.
16. A complementary metal oxide semiconductor (CMOS) structure comprising:
a rotated Si-containing semiconductor substrate having a (100) crystal orientation and a wafer notch along a <100> direction;
at least one pFET located on a surface of said rotated Si-containing semiconductor substrate, said at least one pFET having a channel that is along said <100> direction; and
at least one stressed material located at least within, or on, a surface of said rotated Si-containing semiconductor substrate that induces a stress on said channel of each pFET, wherein when the at least one stressed material includes at least a stressed liner and a stressed well, where the stressed liner is a compressively strained material.