Sub volt flash memory system
Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
1. A sensing system for non-volatile memory comprising:
a plurality of comparators, each comparator including a first input coupled to a reference voltage line, including a second input coupled to a corresponding memory line, and including an output for providing a signal indicative of the difference between the voltages on the first and second inputs, each comparator including a plurality of MOS transistors, some of said plurality of MOS transistors including a bulk voltage terminal, for coupling to a corresponding voltage source generated by a transistor tracking circuit, that is different from a voltage supply of the comparator.
2. The sensing system of claim 1 wherein the voltage of the corresponding voltage source is less than the voltage supply Vdd.
3. The sensing system of claim 1 wherein the voltage of the corresponding voltage source is a bias voltage tracking forward bias pn diode voltage.
4. A differential amplifier for flash memory sensing comprising:
a differential pair comprising a plurality of PMOS transistors and a plurality of NMOS transistors arranged to provide a differential output signal in response to a pair of input signals; and
an output stage coupled to the differential pair to provide an output signal in response to the differential output signal, the output stage comprising a PMOS transistor and an NMOS transistor,
wherein at least one of the PMOS transistors includes a bulk voltage terminal for coupling to a corresponding voltage source, generated by a transistor tracking circuit, that is different from a voltage supply of the differential amplifier.
5. The differential amplifier of claim 4 further comprising a tracking bias circuit coupled to the bulk voltage terminal.
6. A differential amplifier for sensing flash memory comprising:
a differential pair comprising a plurality of PMOS transistors and a plurality of NMOS transistors arranged to provide a differential output signal in response to a pair of input signals;
a bias stage coupled to the PMOS transistors of the differential pair to provide bias to the bulks of the PMOS transistors, generated by a transistor tracking circuit; and
an output stage coupled to the differential pair to provide an output signal in response to the differential output signal, the output stage comprising a PMOS transistor and an NMOS transistor, wherein the PMOS transistor of the output stage includes a bulk voltage terminal for coupling to a voltage source different from a voltage supply of the differential amplifier.
7. A differential amplifier for sensing flash memory comprising:
a differential pair comprising a plurality of PMOS transistors and a plurality of NMOS transistors arranged to provide a differential output signal in response to a pair of input signals;
a bias stage, comprising a transistor tracking circuit, coupled to the NMOS transistors of the differential pair to provide bias to the bulks of the NMOS transistors; and
an output stage coupled to the differential pair to provide an output signal in response to the differential output signal, the output stage comprising a PMOS transistor and an NMOS transistor.
8. The differential amplifier of claim 7 further comprising another bias stage coupled to the PMOS transistors of the differential pair to provide bias to the bulks of the PMOS transistors.
9. The differential amplifier of claim 7 wherein said bias has a predetermined relationship to the input signals.
10. The differential amplifier of claim 7 wherein said bias extends an input common mode voltage range.
11. The differential amplifier of claim 7 wherein said bias reduces threshold of the NMOS input pair at a low level input signal.
12. The differential amplifier of claim 7 wherein said bias increases threshold of the NMOS input pair at a high level input signal.