Memory device and systems and methods for selecting memory cells in the memory device
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.
1. A memory device comprising:
memory sections, each memory section including a plurality of memory cells, wherein the memory sections are arranged in groups of memory sections; and
source lines associated with the groups of memory sections, wherein memory sections included in a first group of memory sections are coupled to a first source line that is distinct from other source lines associated with other groups of memory sections,
wherein for an erase operation of a first memory section in the first group of memory sections, a wordline and a sense gate line corresponding to the first memory section are positioned to provide respective non-zero voltages and wordlines and sense gate lines corresponding to other memory sections in the first group of memory sections are positioned to provide zero voltage, and the first source line is configured to provide a known first voltage while source lines associated with other memory sections are configured to provide a known second voltage that is different from the known first voltage.
2. The memory device of claim 1 , wherein the known first voltage is zero voltage, while the known second voltage is a non-zero voltage.
3. The memory device of claim 1 , wherein the wordline corresponding to the first memory section is positioned to provide a first non-zero voltage and the sense gate line corresponding to the first memory section is positioned to provide a second non-zero voltage that is different from the first non-zero voltage.
4. The memory device of claim 1 , wherein the first group of memory sections includes a plurality of memory sections in a same column of the memory device, and
wherein the plurality of memory sections included in the first group of memory sections correspond to two or more rows of the memory device.
5. The memory device of claim 1 , wherein the first group of memory sections includes a plurality of memory sections corresponding to two or more columns of the memory device, and
wherein the plurality of memory sections included in the first group of memory sections correspond to two or more rows of the memory device.
6. The memory device of claim 1 , wherein a memory section corresponds to a memory byte.
7. The memory device of claim 1 , wherein a memory section is not associated with a byte select transistor.
8. The device of claim 1 , wherein the plurality of memory cells in a memory section are arranged in rows and columns, and wherein the plurality of memory cells in the memory section are selectable by a same wordline while each memory cell in the memory section is selectable by a different bitline.
9. The memory device of claim 8 , wherein a memory cell includes a select transistor and a sense transistor,
wherein the select transistor comprises a gate terminal coupled to a wordline, and a drain terminal coupled to a bitline, and
wherein the sense transistor comprises a gate terminal coupled to a sense gate line, and a source terminal coupled to a source line associated with the memory section that includes the memory cell.
10. The memory device of claim 8 , wherein for a write operation of a memory cell included in the first memory section, a wordline and at least one bitline associated with the first memory section are configured to provide respective non-zero voltages, while a sense gate line associated with the first memory section is configured to provide zero voltage, and
wherein wordlines and sense gate lines corresponding to memory sections in other rows are configured to provide zero voltage.
11. The memory device of claim 10 , wherein the write operation is independent of voltages provided by the first source line and source lines corresponding to the other groups of memory sections.
12. The memory device of claim 1 , wherein the memory device comprises an Electrically Erasable Programmable Read-Only Memory (EEPROM).
13. A system comprising:
a memory device that includes:
memory sections, each memory section including a plurality of memory cells, wherein the memory sections are arranged in groups of memory sections; and
source lines associated with the groups of memory sections, wherein memory sections included in a first group of memory sections are coupled to a first source line that is distinct from other source lines associated with other groups of memory sections; and
instructions stored in a machine-readable medium that, when executed, are configured to cause a processor to perform an erase operation on a first memory section in the first group of memory sections, the erase operation comprising:
providing respective non-zero voltages to a wordline and a sense gate line corresponding to the first memory section and providing zero voltage to wordlines and sense gate lines corresponding to other memory sections in the first group of memory sections; and
providing a known first voltage to the first group of memory sections using the first source line while providing a known second voltage that is different from the known first voltage to other memory sections using source lines associated with the other memory sections.
14. The system of claim 13 , wherein the wordline corresponding to the first memory section is positioned to provide a first non-zero voltage and the sense gate line corresponding to the first memory section is positioned to provide a second non-zero voltage that is different from the first non-zero voltage.
15. The system of claim 13 , wherein the first group of memory sections includes a plurality of memory sections in a same column of the memory device, and
wherein the plurality of memory sections correspond to two or more rows of the memory device.
16. The system of claim 13 , wherein the first group of memory sections includes a plurality of memory sections corresponding to two or more columns of the memory device, and
wherein the plurality of memory sections included in the first group of memory sections correspond to two or more rows of the memory device.
17. The system of claim 13 , wherein a memory section is not associated with a byte select transistor.
18. The system of claim 13 , wherein the plurality of memory cells in a memory section are arranged in rows and columns, and wherein the plurality of memory cells in the memory section are selectable by a same wordline while each memory cell in the memory section is selectable by a different bitline.
19. The system of claim 18 , wherein a memory cell includes a select transistor and a sense transistor,
wherein the select transistor comprises a gate terminal coupled to a wordline, and a drain terminal coupled to a bitline, and
wherein the sense transistor comprises a gate terminal coupled to a sense gate line, and a source terminal coupled to a source line associated with the memory section that includes the memory cell.
20. The system of claim 18 , wherein the instructions are further configured to cause the processor to perform a write operation of a first memory cell in the first memory section, the write operation comprising:
providing non-zero voltages to a wordline and at least one bitline associated with the first memory section, while providing zero voltage to a sense gate line associated with the first memory section; and
providing zero voltage to wordlines and sense gate lines corresponding to memory sections in other rows.
21. The system of claim 20 , wherein the write operation is independent of voltages provided by the first source line and source lines corresponding to the other groups of memory sections.