IP Library Granted Patent US 9,953,886
Granted Patent B2
US 9,953,886 · App. 15/242,051 · Granted Apr 24, 2018

Single-wafer real-time etch rate and uniformity predictor for plasma etch processes

Inventors: Justin Hiroki Sato (West Linn, OR); Brian Dee Hennes (Portland, OR); Yannick Carll Kimmel (New York, NY)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H01L22/12H01J37/32935H01J37/32963H01L21/0274H01L21/02164H01L21/3065H01L21/3081H01J2237/334H01J2237/3343
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Quick Facts
Patent No.
US 9,953,886
App. No.
15/242,051
Granted
Apr 24, 2018
Kind
B2
Abstract

The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A method for testing a semiconductor plasma etch chamber may include: depositing a film on a substrate of a wafer, the wafer including a center region and an edge region; depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer; and performing an etch process on the wafer that includes at least three process steps. The three process steps may include: etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved; performing an in-situ ash to remove any photoresist; and etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved. The method may further include determining whether both endpoints are achieved within respective previously set tolerances, and, if both endpoints are achieved within the previously set tolerance, qualifying the plasma etch chamber as verified.

Claims (41)

1. A method for testing a semiconductor plasma etch chamber, the method comprising:

depositing a film on a substrate of a wafer, the wafer including a center region and an edge region;

depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer;

performing an etch process on the wafer that includes at least three process steps, the at least three process steps including:

etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved;

after the first clear endpoint signal is achieved, performing an in-situ ash to remove any photoresist; and

after performing an in-situ ash, etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved;

determining whether both endpoints are achieved within respective previously set tolerances; and

if both endpoints are achieved within the previously set tolerance, qualifying the plasma etch chamber as verified.

2. A method according to claim 1 , wherein the photoresist is deposited in a pattern that covers the film disposed in the center region of the wafer and exposes the film deposited in the edge region of the wafer.

3. A method according to claim 1 , wherein the previously set tolerance corresponding to the first clear endpoint reflects an edge etch rate for the plasma chamber.

4. A method according to claim 1 , wherein the previously set tolerance corresponding to the second clear endpoint reflects a center etch rate for the plasma chamber.

5. A method according to claim 1 , further comprising measuring the film after it is deposited on the substrate and before depositing the photoresist.

6. A method according to claim 1 , wherein the wafer is stored for up to three months after deposition of the photoresist and before preforming the etch process.

7. A method according to claim 1 , wherein the film comprises silicon dioxide.

8. A method according to claim 1 , further comprising printing the photoresist with a mask-less photolithography process.

9. A method according to claim 1 , further comprising measuring the thickness of the film to compare to a predetermined tolerance before depositing the photoresist.

10. A method for testing an etch rate uniformity for a plasma etch chamber, the method comprising:

etching an exposed portion of film on an edge region of a wafer, while a center region of the wafer is protected by photoresist and recording an etch rate for the edge region;

after etching the exposed portion of film on the edge region, performing an ash process to remove the photoresist form the center region of the wafer; and

after performing the ash process, etching the center region of the wafer and recording an etch rate for the center region.

11. A method according to claim 10 , further comprising comparing the etch rate for the edge region and the etch rate for the center region against respective predetermined thresholds.

12. A method according to claim 11 , further comprising approving the plasma chamber as qualified if both etch rates fall within the respective predetermined thresholds.

13. A method according to claim 10 , further comprising depositing the film on the wafer.

14. A method according to claim 10 , further comprising:

depositing the film on the wafer; and

depositing photoresist on the film in a pattern that exposes the edge region of the wafer and the film thereon.

15. A method according to claim 10 , wherein the film comprises silicon dioxide.

16. A method according to claim 10 , further comprising:

depositing the film on the wafer; and

measuring the thickness of the film to compare to a predetermined tolerance.

17. A method for testing a semiconductor plasma etch chamber, the method comprising:

depositing a film on a substrate of a wafer, the wafer including a center region and an edge region;

depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer;

performing an etch process on the wafer that includes at least three process steps, the at least three process steps including:

etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved;

performing an in-situ ash to remove any photoresist; and

etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved;

determining whether both endpoints are achieved within respective previously set tolerances; and

if both endpoints are achieved within the previously set tolerance, qualifying the plasma etch chamber as verified,

wherein the wafer is stored for up to three months after deposition of the photoresist and before preforming the etch process.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2016
From: SATO, JUSTIN HIROKI; HENNES, BRIAN DEE; KIMMEL, YANNICK CARLL
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 040232/0871 →
Continuity (2)
Provisional Application 62208295 · Aug 21, 2015
Related Publication 20170053841A1 · Feb 23, 2017