IP Library Granted Patent US 10,176,076
Granted Patent B2
US 10,176,076 · App. 15/343,666 · Granted Jan 8, 2019

Breaking code execution based on time consumption

Inventor: Ingar Hanssen (Trondheim, NO)
Assignee: Atmel Corporation
G06F11/362G06F11/348G06F11/3419G06F11/3604G06F11/3612G06F11/3636G06F11/3648
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Quick Facts
Patent No.
US 10,176,076
App. No.
15/343,666
Granted
Jan 8, 2019
Kind
B2
Abstract

An on-chip system uses a time measurement circuit to trap code that takes longer than expected to execute by breaking code execution on excess time consumption.

Claims (37)

1. A method of breaking code execution in a device, the method comprising:

receiving, during execution of a code segment on a device, a first signal indicating a start point specified in the code segment;

in response to receiving the first signal, starting a counter in a time measurement circuit included in the device;

comparing, using a first comparator included in the device, a count value from the counter to a first count representing a first time setting, wherein the first time setting includes a maximum time setting stored in a register included in the device:

upon the count value satisfying a first condition based on comparing to the first count, triggering a first break event corresponding to the execution of the code segment, wherein the first condition includes the count value exceeding the first count representing the maximum time setting:

receiving, during execution of the code segment on the device, a second signal indicating a stop point specified in the code segment;

in response to receiving the second signal, stopping the counter;

comparing, using a second comparator included in the device, the count value from the counter to a second count representing a second time setting; and

upon the count value satisfying a second condition based on comparing to the second count, triggering a second break event corresponding to the execution of the code segment.

2. The method of claim 1 , wherein the second time setting includes a minimum time setting stored in a register included in the device and wherein the second condition includes the count value being less than the second count representing the minimum time setting.

3. The method of claim 1 , wherein the start point and the stop point are defined in the code segment by one of code instrumentation, or instruction fetch address comparators.

4. The method of claim 1 , wherein triggering the first break event includes generating a signal indicating one of a program break or a maximum time event.

5. The method of claim 1 , wherein triggering the second break event includes generating a signal indicating one of a program break or a minimum time event.

6. The method of claim 1 , wherein the device includes a microcontroller.

7. The method of claim 1 , further comprising:

generating, using a debug or event system, a program break or time event, respectively, based on a comparison of the count value from the counter to the first count representing the first time setting or the second count representing the second time setting.

8. The method of claim 1 , further comprising:

counting, using an interrupt level counter, interrupt levels for nested interrupt signals.

9. The method of claim 1 , wherein at least one of the first time setting or the second time setting is configured by a user.

10. A device comprising:

a time measurement circuit including a counter, a first comparator coupled to the counter and a second comparator coupled to the counter, wherein the time measurement circuit is configured to:

receive, during execution of a code segment on the device, a first signal indicating a start point specified in the code segment;

in response to receiving the first signal, start the counter; compare, using the first comparator, a count value from the counter to a first count representing a first time setting, wherein the first time setting includes a maximum time setting stored in a register;

upon the count value satisfying a first condition based on comparing to the first count, trigger a first break event corresponding to the execution of the code segment wherein the first condition includes the count value exceeding the first count representing the maximum time setting:

receive, during execution of the code segment on the device, a second signal indicating a stop point specified in the code segment;

in response to receiving the second signal, stop the counter; compare, using the second comparator, the count value from the counter to a second count representing a second time setting; and

upon the count value satisfying a second condition based on comparing to the second count, trigger a second break event corresponding to the execution of the code segment.

11. The device of claim 10 , wherein the second time setting includes a minimum time setting stored in a register and wherein the second condition includes the count value being less than the second count representing the minimum time setting.

12. The device of claim 10 , wherein the start point and the stop point are defined in the code segment by one of code instrumentation, or instruction fetch address comparators.

13. The device of claim 10 , wherein triggering the first break event includes generating a signal indicating one of a program break or a maximum time event.

14. The device of claim 10 , wherein triggering the second break event includes generating a signal indicating one of a program break or a minimum time event.

15. The device of claim 10 , wherein the device includes a microcontroller.

16. The device of claim 10 , further comprising:

a debug or event system coupled to the time measurement circuit and configured to generate a program break or time event, respectively, based on a comparison of the count value from the counter to the first count representing the first time setting or the second count representing the second time setting.

17. The device of claim 10 , further comprising:

an interrupt level counter coupled to the counter and configured to count interrupt levels for nested interrupt signals.

18. The device of claim 10 , wherein at least one of the first time setting or the second time setting is configured by a user.

Assignments (15)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2018
From: HANSSEN, INGAR
To: ATMEL CORPORATION
Reel/Frame 044819/0179 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
Continuity (2)
Continuation 13974965 · Aug 23, 2013
Related Publication 20170060727A1 · Mar 2, 2017