IP Library Granted Patent US 9,887,206
Granted Patent B2
US 9,887,206 · App. 15/453,829 · Granted Feb 6, 2018

Method of making split gate non-volatile memory cell with 3D FinFET structure

Inventors: Chien-Sheng Su (Saratoga, CA); Jeng-Wei Yang (Zhubei, TW); Man-Tang Wu (Hsinchu County, TW); Chun-Ming Chen (New Taipei, TW); Hieu Van Tran (San Jose, CA); Nhan Do (Saratoga, CA)
Assignee: Silicon Storage Technology, Inc.
H01L27/11521H01L21/28273H01L29/0847H01L29/66795H01L29/66825H01L29/7856H01L29/7881
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Quick Facts
Patent No.
US 9,887,206
App. No.
15/453,829
Granted
Feb 6, 2018
Kind
B2
Abstract

A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Claims (32)

1. A method of forming a non-volatile memory cell, comprising:

forming a pair of parallel trenches into a surface of a semiconductor substrate of a first conductivity type, resulting in a fin shaped upper surface portion between the trenches having a top surface and two side surfaces;

forming insulation material along the top surface and the two side surfaces;

forming spaced apart first and second regions of a second conductivity type different than the first conductivity type in the fin shaped upper surface portion, with a channel region extending between the first region and the second region;

wherein the channel region has a first portion that includes a first portion of the top surface and first portions of the two side surfaces, and has a second portion that includes a second portion of the top surface and second portions of the two side surfaces,

forming a conductive floating gate that includes:

a first portion that extends along and is insulated from the first portion of the top surface,

a second portion that extends along and is insulated from the first portion of one of the two side surfaces, and

a third portion that extends along and is insulated from the first portion of the other of the two side surfaces;

forming a conductive control gate that includes:

a first portion that extends along and is insulated from the second portion of the top surface,

a second portion that extends along and is insulated from the second portion of one of the two side surfaces,

a third portion that extends along and is insulated from the second portion of the other of the two side surfaces,

a fourth portion that extends up and over and is insulated from at least some of the floating gate first portion,

a fifth portion that extends out and over and is insulated from at least some of the floating gate second portion, and

a sixth portion that extends out and over and is insulated from at least some of the floating gate third portion.

2. The method of claim 1 , wherein the forming of the pair of trenches includes:

forming a block of material over the surface of the substrate;

etching portions of the substrate adjacent to the block of material leaving the fin shaped upper surface portion underneath the block of material.

3. The method of claim 2 , wherein the forming of the block of material includes:

forming a layer of material on the surface of the substrate;

forming a second block of material on the layer of material;

forming a spacer of material on the layer of material and along a side surface of the second block of material;

removing the second block of material;

etching portions of the layer of material adjacent to the spacer of material leaving the block of material underneath the spacer of material.

4. The method of claim 2 , wherein the forming of the block of material includes:

forming a layer of material on the surface of the substrate;

forming photo resist over the layer of material;

performing a photolithography exposure and etch to selectively remove portions of the photo resist leaving a block of the photo resist on the layer of material;

etching portions of the layer of material adjacent to the block of photo resist leaving the block of material underneath the block of photo resist.

5. The method of claim 1 , further comprising:

oxidizing a top surface of the floating gate to form oxidized polysilicon such that the top surface of the floating gate becomes sloping and terminates in a sharp edge that faces and is insulated from the control gate.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
Continuity (3)
Division 15050309 · Feb 22, 2016
Provisional Application 62134489 · Mar 17, 2015
Related Publication 20170179141A1 · Jun 22, 2017