Three-dimensional memory device including crack-resistant backside passivation structure and methods of forming the same
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a three-dimensional array of memory elements embedded in the alternating stack, a dielectric material portion located adjacent to the alternating stack, connection via structures vertically extending through the dielectric material portion, a backside connection pad cavity vertically extending through the source layer, a backside isolation layer, and a backside connection pad structure including a proximal portion contacting end surfaces of the connection via structures. The backside connection pad structure includes a tapered connecting portion overlying a stepped connecting portion of the backside isolation layer, or dummy regions which do not contact the end surfaces of the connection via structures.
1 . A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a first side of a source layer;
a three-dimensional array of memory elements embedded in the alternating stack;
a dielectric material portion located over the first side of the source layer adjacent to the alternating stack;
connection via structures vertically extending through the dielectric material portion;
a backside connection pad cavity vertically extending through the source layer;
a backside isolation layer comprising a first horizontally-extending portion located within the backside connection pad cavity and comprising a first inner sidewall having a first proximal edge that is in contact with a horizontal surface of the dielectric material portion and having a first distal edge that is spaced from the dielectric material portion by a vertical thickness of the first horizontally-extending portion, a second horizontally-extending portion that is located over a second side of the source layer, and a connecting portion that connects the first horizontally-extending portion and the second horizontally-extending portion and that comprises a second inner sidewall having a second distal edge that is adjoined to a distal horizontal surface of the second horizontally-extending portion; and
a backside connection pad structure comprising a proximal portion contacting end surfaces of the connection via structures, a distal portion located over the second horizontally-extending portion of the backside isolation layer, and a connecting portion that connects the proximal portion and the distal portion, wherein a lateral distance between an inner sidewall and an outer sidewall of the connecting portion of the backside connection pad structure within a first horizontal plane containing the second distal edge is greater than a lateral distance between the first distal edge and the second distal edge of the backside isolation layer.
2 . The memory device of claim 1 , wherein:
the alternating stack, the three-dimensional array of memory elements, the connection via structures, the backside isolation layer, and the backside connection pad structure are provided in a memory die which further comprises memory-side bonding pads;
the three-dimensional memory device further comprises a logic die that comprises logic-side bonding pads and a peripheral circuit configured to control operation of the three-dimensional array of memory elements; and
the logic-side bonding pads are bonded to the memory-side bonding pads.
3 . The memory device of claim 1 , further comprising backside dielectric layers located over the second side of the source layer, wherein:
a proximal horizontal surface of the second horizontally-extending portion of the backside isolation layer contacts a distal horizontal surface of the backside dielectric layers; and
an outer sidewall of the connecting portion of the backside isolation layer contacts sidewalls of the backside dielectric layers.
4 . The memory device of claim 3 , further comprising a source connection pad structure vertically extending through the backside dielectric layers and the backside isolation layer and contacting a horizontal surface of the source layer and having a same material composition as the backside connection pad structure.
5 . The memory device of claim 1 , wherein the first horizontally-extending portion of the backside isolation layer comprises moat-shaped opening laterally surrounding a backside isolation plate located in a center region of the backside connection pad cavity and contacting a horizontal surface of the dielectric material portion.
6 . The memory device of claim 5 , wherein:
first regions of the proximal portion of the backside connection pad structure which contact the end surfaces of the connection via structures are located within first strip regions of the moat-shaped opening; and
dummy second regions of the proximal portion of the backside connection pad structure which do not contact the end surfaces of the connection via structures are located within second strip regions of the moat-shaped opening.
7 . The memory device of claim 5 , wherein the backside connection pad structure contacts an entirety of a distal horizontal surface of the backside isolation plate and laterally surrounds and encloses the backside isolation plate, such that the backside isolation plate is laterally spaced from the backside isolation layer by the backside connection pad structure.
8 . The memory device of claim 1 , wherein the first horizontally-extending portion of the backside isolation layer comprises:
a first-type opening laterally surrounding a first region of the proximal portion of the backside connection pad structure which contacts the end surfaces of the connection via structures; and
a second-type opening laterally surrounding a dummy second region of the proximal portion of the backside connection pad structure which does not contact the end surfaces of the connection via structures, wherein an entirety of a horizontal surface of the dummy second region located within an area of the second-type opening is in contact with a surface segment of the dielectric material portion.
9 . The memory device of claim 8 , wherein the first horizontally-extending portion of the backside isolation layer comprises:
at least one additional first-type opening laterally surrounding a respective additional first region of the proximal portion of the backside connection pad structure, the respective additional first region contacting respective end surfaces of additional connection via structures embedded in the dielectric material portion; and
at least one additional second-type opening laterally surrounding a respective additional dummy second region of the proximal portion of the backside connection pad structure, wherein an entirety of a horizontal surface of the respective additional second region located within an area of a respective one of the at least one additional second-type opening is in contact with a respective additional surface segment of the dielectric material portion.
10 . The memory device of claim 1 , further comprising:
at least one passivation dielectric layer contacting a first segment of a distal surface of the backside connection pad structure and contacting a distal surface of the backside isolation layer; and
a backside contact pad vertically extending through the at least one passivation dielectric layer and contacting a second segment of the distal surface of the backside connection pad structure.
11 . The memory device of claim 10 , wherein a proximal portion of the backside connection pad structure that is contacted by the backside contact pad is vertically spaced from the dielectric material portion by a horizontally-extending portion of the backside isolation layer.
12 . The memory device of claim 10 , wherein a proximal portion of the backside connection pad structure that is contacted by the backside contact pad is vertically spaced from the dielectric material portion by a backside isolation plate having a same material composition and a same thickness as the second horizontally-extending portion of the backside isolation layer and that is laterally spaced from the backside isolation layer by a ring-shaped region of the backside connection pad structure that contacts the dielectric material portion and laterally surrounds the backside isolation plate.
13 . The memory device of claim 1 , wherein:
the connecting portion of the backside connection pad structure comprises a first inner sidewall segment adjoined to the proximal portion of the backside connection pad structure and a second inner sidewall segment adjoined to the distal portion of the backside connection pad structure;
the first inner sidewall segment has first taper angle a 1 with respect to a vertical direction; and
the second inner sidewall segment has a second taper angle a 2 with respect to the vertical direction that is smaller than the first taper angle a 1 .
14 . The memory device of claim 1 , wherein:
the connecting portion of the backside isolation layer comprises a stepped inner sidewall comprising plurality of horizontally-extending surface segments and a plurality of vertically-extending surface segments; and
the connecting portion of the backside connection pad structure comprises a stepped outer sidewall comprising plurality of horizontally-extending surface segments and a plurality of vertically-extending surface segments.
15 . A method of forming a device structure, comprising:
forming a combination of a three-dimensional memory array and a dielectric material portion over a first side of a source layer that overlies a carrier substrate, wherein the three-dimensional memory array comprises a three-dimensional array of memory elements embedded in an alternating stack of insulating layers and electrically conductive layers, and the dielectric material portion is located adjacent to the alternating stack;
forming connection via structures through the dielectric material portion;
removing the carrier substrate;
forming a backside connection pad cavity through at least the source layer after removing the carrier substrate;
depositing and patterning a backside isolation layer, wherein the backside isolation layer comprises a first horizontally-extending portion located within the backside connection pad cavity and comprising a first inner sidewall having a first proximal edge that is in contact with a horizontal surface of the dielectric material portion and having a first distal edge that is spaced from the dielectric material portion by a vertical thickness of the first horizontally-extending portion, a second horizontally-extending portion that is located over a second side of the source layer, and a connecting portion that connects the first horizontally-extending portion and the second horizontally-extending portion and that comprises a second inner sidewall having a second distal edge that is adjoined to a distal horizontal surface of the second horizontally-extending portion; and
forming a backside connection pad structure, wherein the backside connection pad structure comprises a proximal portion contacting end surfaces of the connection via structures, a distal portion located over the second horizontally-extending portion of the backside isolation layer, and a connecting portion that connects the proximal portion and the distal portion, wherein a lateral distance between an inner sidewall and an outer sidewall of the connecting portion of the backside connection pad structure within a first horizontal plane containing the second distal edge is greater than a lateral distance between the first distal edge and the second distal edge of the backside isolation layer.
16 . The method of claim 15 , wherein:
the backside isolation layer is deposited directly on a sidewall of the source layer and directly on the end surfaces of the connection via structures; and
at least one discrete opening is formed through the backside isolation layer, wherein the end surfaces of the connection via structures are exposed within one of the at least one discrete opening upon patterning the backside isolation layer.
17 . The method of claim 15 , wherein:
the second inner sidewall of the backside isolation layer is formed during the depositing of the backside isolation layer; and
the first inner sidewall of the backside isolation layer is formed during the patterning of the backside isolation layer.
18 . The method of claim 15 , wherein:
the alternating stack, the three-dimensional array of memory elements, and the connection via structures are formed in a memory die which further comprises memory-side bonding pads; and
the method further comprises providing a logic die that comprises logic-side bonding pads and a peripheral circuit configured to control operation of the three-dimensional array of memory elements, and bonding the logic die to the memory die by bonding the logic-side bonding pads to the memory-side bonding pads.
19 . The method of claim 15 , further comprising forming backside dielectric layers over the second side of the source layer, wherein:
a proximal horizontal surface of the second horizontally-extending portion of the backside isolation layer is formed directly on a distal horizontal surface of the backside dielectric layers; and
an outer sidewall of the connecting portion of the backside isolation layer is formed directly on sidewalls of the backside dielectric layers.
20 . The method of claim 19 , further comprising forming a source connection pad structure through the backside dielectric layers and the backside isolation layer directly on a horizontal surface of the source layer, wherein the source connection pad structure has a same material composition as the backside connection pad structure.