Self-learning built-in self-test (BIST) for leak detection in non-volatile memory
In a word line leakage detection process in a NAND or other non-volatile memory device, to determine leaky blocks of a memory device, a reference value for block is determined by comparing the current drawn by the peripheral circuitry of the block with a sequence of comparison current values, corresponding to a range of digital values, while the peripheral circuit is not connected to the block. The current drawn when the peripheral circuitry is connected to the block is then determined, again by comparison with a sequence of comparison values, but of a reduced range of digital values, running from an offset above the reference value to an offset below the reference value. To further reduce test times, the same reference value is used for a group of blocks, such as groups of blocks that share a set of supply lines.
1 . A non-volatile memory system, comprising:
a control circuit configured to connect to an array comprising a plurality of blocks, including a first plurality of blocks, of non-volatile memory cells, the control circuit comprising:
bias circuitry configured to selectively bias the plurality of blocks for memory operations, including testing for current leakage; and
built-in self-test circuitry to test for current leakage from the plurality of blocks, where, to test for current leakage in the array, the built-in self-test circuitry is configured to:
with the bias circuitry configured to perform a leak test on a selected block of the first plurality of blocks, but disconnected from the selected block of the first plurality of blocks, determine a first reference current value for the selected block by comparing a current drawn with a sequence of comparison current values;
with the bias circuitry configured to perform a leak test on the selected block and connected to the selected block, determine a leakage current value for the selected block by comparing a current drawn with a first sub-sequence of comparison current values, the first sub-sequence formed of a sequence between the determined first reference current value offset upward by a first offset number of comparison current values and the determined first reference current value offset downward by a second offset number of comparison current values, the first sub-sequence of comparison values being a proper subset of the sequence of comparison current values;
compare the first reference current value for the selected block with the determined leakage current value for the selected block; and
based on comparing the first reference current value for the selected block with the determined leakage current value for the selected block, determine whether the selected block is defective.
2 . The non-volatile memory system of claim 1 , wherein the control circuit is formed on a control die, the non-volatile memory system further comprising:
a memory die including the array, the memory die separate from and bonded to the control die.
3 . The non-volatile memory system of claim 1 , wherein:
the sequence of comparison current values are a set of analog current values corresponding to a monotonic sequence of digital values.
4 . The non-volatile memory system of claim 3 , wherein:
the sequence of digital values corresponding to the sequence of comparison current values is a monotonically decreasing sequence; and
the first sub-sequence of comparison values is a monotonically decreasing sub-sequence digital values running from a first value offset by a first number of digital values above the digital value corresponding to the reference current to a second value offset by a second number of digital values below the digital value corresponding to the reference current.
5 . The non-volatile memory system of claim 4 , wherein the first number of digital values and the second number of digital values are user settable.
6 . The non-volatile memory system of claim 4 , wherein the first number of digital values and the second number of digital values are determined as part of a device characterization process.
7 . The non-volatile memory system of claim 1 , wherein to test for current leakage in the array, the built-in self-test circuitry is further configured, for each additional block of the first plurality of blocks other than the first block, to:
with the bias circuitry configured to perform a leak test on the additional block and connected to the first additional block, determine a leakage current value for the additional block by comparing a current drawn with the first sub-sequence of comparison current values;
compare the first reference current value for the first block with the determined leakage current value for the additional block; and
based on comparing the first reference current value for the first block with the determined leakage current value for the additional block, determine whether the additional block is defective.
8 . The non-volatile memory system of claim 7 , wherein the array further comprises one or more second plurality of blocks of non-volatile memory cells, and wherein to test for current leakage in the array, the built-in self-test circuitry is further configured, for each of second plurality of blocks, to:
with the bias circuitry configured to perform a leak test on a reference block of the second plurality of blocks, but disconnected from the reference block, determine a corresponding reference current value for the second plurality of blocks by comparing a current drawn with the sequence of comparison current values; and
for each of blocks of the second plurality of blocks:
with the bias circuitry configured to perform a leak test on the selected block and connected to the selected block, determine a leakage current value for the selected block by comparing a current drawn with a second sub-sequence of comparison current values, the second sub-sequence formed of a sequence between the determined corresponding reference current value offset upward by the first offset number of comparison current values and the determined corresponding reference current value offset downward by the second offset number of comparison current values, the second sub-sequence of comparison values being a proper subset of the sequence of comparison current values;
compare the corresponding reference current value for the second plurality of blocks with the determined leakage current value for the selected block; and
based on comparing the reference current value for the second plurality of blocks with the determined leakage current value for the selected block, determine whether the additional block is defective.
9 . The non-volatile memory system of claim 8 , wherein the bias circuitry is configured to provide to bias voltages independently to the first plurality of blocks and to each of the one or more second plurality of blocks as a group.
10 . The non-volatile memory system of claim 8 , further comprising:
the array, wherein each of the first plurality of blocks and each of the one or more second plurality of blocks are a physically contiguous plurality of blocks.
11 . The non-volatile memory system of claim 1 , further comprising:
the array, wherein the array has a NAND architecture, each of the plurality of blocks comprises a plurality of word lines along which the memory cells, and where the leak test includes a test for word line to word line leakage.
12 . The non-volatile memory system of claim 1 , further comprising:
the array, wherein the array has a three dimensional NAND architecture in which NAND strings are formed along memory holes, each of the plurality of blocks comprises a plurality of word lines along which the memory cells, and where the leak test includes a test for word line to memory hole leakage.
13 . A method, comprising:
determining, for a first block of each of a plurality of groups of blocks of an array of non-volatile memory cells of a non-volatile memory device, a corresponding reference current value by:
with biasing circuitry of the memory device configured to perform a leakage test on, but while disconnected from the memory cells of, the first block, comparing a resultant current level with a first sequence of comparison voltage level each corresponding to one of a first sequence of digital values; and
based on the comparison of the resultant current level with the first sequence of comparison voltage level, determining a digital value for the corresponding reference current value of the group of blocks;
determining, for each block of each of the plurality of groups of blocks, a corresponding leakage current value by, for each group of blocks:
with the biasing circuitry of the memory device connected to memory cells of, and configured to perform a leakage test on, a selected block of the plurality of the groups of blocks, comparing a resultant current level with a second sequence of comparison voltage level each corresponding to one of a second sequence of digital values; and
based on the comparison of the resultant current level with the second sequence of comparison voltage level, determining a digital value for the corresponding leakage current value of the selected block; and
determining, for each block of each of the plurality of groups of blocks, either a pass status or a fail status by, for each group of blocks:
comparing the digital value for the corresponding leakage current value of the selected block with the digital value for the corresponding reference current value of the group of blocks.
14 . The method of claim 13 , wherein, for each of the groups of blocks, the second sequence of digital values is a proper subset of the first sequence of digital values and is formed of a sequence of digital values between the digital value for the corresponding reference current value offset upward by a first number of the digital values and the digital value for the corresponding reference current value offset downward by a second number of the digital values, wherein the first number of digital values is a same for all of the groups of blocks and the second number of digital values is a same all of the groups of blocks.
15 . The method of claim 13 , further comprising:
storing, for each of the groups of blocks, the digital value for the corresponding reference current value of the group of blocks in a first register; and
storing, for each block of each of the groups of blocks, the digital value for the corresponding leakage current value in a second register,
wherein comparing the digital value for the corresponding leakage current value of the selected block with the digital value for the corresponding reference current value of the group of blocks comprises comparing a value stored in the first register with a value stored in the second register.
16 . The method of claim 13 , wherein the biasing circuit of the memory device includes a set of switches shared by the blocks of each group of the plurality of groups, but distinct from a set of switches shared by the blocks of each of the other groups of the plurality of groups.
17 . A non-volatile memory system, comprising:
an array of non-volatile memory cells comprising a plurality of groups of blocks of non-volatile memory cells; and
one or more control circuits connected to the array, comprising:
biasing circuitry configured to selectively bias the blocks for memory operations, including testing for current leakage, including a separate set of switches for supplying voltage levels for each group of blocks;
built-in self-test circuitry, where to perform current leakage testing on the blocks, the built-in self-test circuitry is configured to:
determine, for a first block of each of a plurality of groups, a corresponding reference current value by:
with the biasing circuitry configured to perform a leakage test on, but while disconnected from the memory cells of, the first block, comparing a resultant current level with a first sequence of comparison voltage level each corresponding to one of a first sequence of digital values; and
based on the comparison of the resultant current level with the first sequence of comparison voltage level, determining a digital value for the corresponding reference current value of the group of blocks;
determine, for each block of each of the plurality of groups of blocks, a corresponding leakage current value by:
with the biasing circuitry connected to memory cells of, and configured to perform a leakage test on, said each block, comparing a resultant current level with a second sequence of comparison voltage level each corresponding to one of a second sequence of digital values; and
based on the comparison of the resultant current level with the second sequence of comparison voltage level, determining a digital value for the corresponding leakage current value of said each block; and
determine, for each block of each of the plurality of groups of blocks, either a pass status or a fail status by, for each group of blocks by:
comparing the digital value for the corresponding leakage current value of said each block with the digital value for the corresponding reference current value of the group of blocks.
18 . The non-volatile memory system of claim 17 , wherein, for each of the groups of blocks, the second sequence of digital values is a proper subset of the first sequence of digital values and is formed of a sequence of digital values between the digital value for the corresponding reference current value offset upward by a first number of the digital values and the digital value for the corresponding reference current value offset downward by a second number of the digital values, wherein the first number of digital values is the same for all of the groups of blocks and the second number of digital values is the same all of the groups of blocks.
19 . The non-volatile memory system of claim 17 , wherein the built-in self-test circuitry comprises:
a first register;
a second register; and
a comparator,
wherein the built-in self-test circuitry is further configured to:
store, for each of the groups of blocks, the digital value for the corresponding reference current value of the group of blocks in a first register; and
storing, for each block of each of the groups of blocks, the digital value for the corresponding leakage current value in a second register,
wherein comparing the digital value for the corresponding leakage current value of said each block with the digital value for the corresponding reference current value of the group of blocks comprises comparing a value stored in the first register with a value stored in the second register.
20 . The non-volatile memory system of claim 17 , wherein:
the array of non-volatile memory cells has a three dimensional NAND architecture in which NAND strings are formed along memory holes, each of the blocks comprises a plurality of word lines along which the memory cells, and where the leak test includes a test for word line leakage.