Self-aligned bipolar transistor
View Patent ↗A heterojunction bipolar transistor with self-aligned features having a self-aligned dielectric sidewall spacer disposed between base contact and emitter contact, and self-aligned base mesa aligned relative to self-aligned base contact. The base contact is self-aligned relative to the self-aligned dielectric sidewall spacer providing a predetermined base-to-emitter spacing thereby. The emitter may be an n-type, InP material; the base can be a p-type InGaAs material, possibly carbon-doped. The fabrication method includes forming a emitter electrode on an emitter layer; using the emitter contact as a mask, anisotropically etching the emitter exposing the base layer; forming a self-aligned dielectric sidewall spacer upon the emitter and base; self-alignedly depositing a self-aligned base electrode; using the self-aligned base electrode as a mask, anisotropically etching the base layer to expose the subcollector; and depositing a collector electrode on the subcollector layer.
1. A semiconductor structure, comprising:
a collector, a base, and an emitter, operably coupled as a bipolar junction transistor;
a dielectric sidewall spacer with a predetermined spacer thickness self-alignedly disposed on a side wall of the emitter;
a base contact seif-alignedly disposed upon the dielectric sidewall spacer and electrically coupled with the base;
a self-aligned base mesa defined by the base contact; and
a base metal contact pad on the base mesa, the base metal contact pad contacting the dielectric sidewall spacer.
2. The semiconductor structure of claim 1 , wherein the collector, the emitter, and the base are comprised of materials from the Group III-V compound semiconductor group materials.
3. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a heterojunction bipolar transistor having an InP/InGaAs heterojunction.
4. The semiconductor structure of claim 3 , wherein the base is a InGaAs material and the emitter is an InP material.
5. The semiconductor structure of claim 4 , wherein the base is carbon-doped.
6. A semiconductor structure, comprising:
a collector, a base, and an emitter, operably coupled as a bipolar junction transistor;
a dielectric sidewall spacer self-alignedly disposed on the emitter;
a base contact self-alignedly disposed upon the dielectric sidewall spacer and electrically coupled with the base;
a base mesa self-aligned relative to the base contact; and
a base metal contact pad overlaying a portion of the emitter, the base metal contact pad electrically coupled with the base contact.
7. The semiconductor structure of claim 6 further comprising a substrate, the substrate underlying the collector, and a via extending through the substrate to a subcollector layer of the collector.
8. A semiconductor structure, comprising:
a collector, a base, and an emitter, operably coupled as a bipolar junction transistor;
a dielectric sidewall spacer with a predetermined spacer thickness self-alignedly disposed on a side wall of the emitter;
a base contact self-alignedly disposed upon the dielectric sidewall spacer and electrically coupled with the base; a self-aligned base mesa defined by the base contact;
a substrate, the substrate underlying the collector, and a via extending through the substrate to a subcollector layer of the collector.
9. A heterojunction bipolar transistor, comprising:
a dielectric sidewall spacer with a predetermined spacer thickness self-alignedly disposed on a wall of an emitter;
a base contact self-aligned relative to the dielectric sidewall spacer, the dielectric sidewall spacer providing a self-aligned predetermined base-to-emitter spacing;
a self-aligned base mesa defined by the base contact; and
a base metal contact pad on the base mesa, the base metal contact pad contacting the dielectric sidewall spacer.
10. A heterojunction bipolar transistor, comprising:
a dielectric sidewall spacer self-alignedly disposed on a wall of an emitter;
a base contact self-aligned relative to the dielectric sidewall spacer, the dielectric sidewall spacer providing a self-aligned base-to-emitter spacing;
a base mesa self-aligned relative to the base contact; and
a base metal contact pad overlaying a portion of the emitter, the base metal contact pad electrically coupled with the base contact.
11. A signal amplifier, comprising:
a collector;
a collector contact electrically coupled with the collector;
an emitter being a Group III-V semiconductor material of a first conductivity type;
an emitter contact electrically coupled with the emitter; a base electrically coupled with the collector and the emitter, and being a Group III-V semiconductor material of a second conductivity type;
a self-aligned base contact electrically coupled with the base;
a self-aligned dielectric sidewall spacer with a predetermined spacer thickness disposed between the base contact and the emitter, wherein the base contact is self-aligned relative to the self-aligned dielectric sidewall spacer and a predetermined base-to-emitter spacing is provided thereby; and
a self-aligned base mesa defined by the base contact; and
a base metal contact pad on the base mesa, the base metal contact pad contacting the dielectric sidewall spacer.
12. The signal amplifier of claim 11 , wherein the base comprises a p-type InGaAs material and the emitter comprises an n-type InP material.
13. The signal amplifier of claim 11 , wherein the base comprises an n-type material and the emitter comprises an p-type material.
14. A signal amplifier, comprising:
a collector;
a collector contact electrically coupled with the collector;
an emitter being a Group III-V semiconductor material of a first conductivity type;
an emitter contact electrically coupled with the emitter; a base electrically coupled with the collector and the emitter, and being a Group III-V semiconductor material of a second conductivity type;
a base contact electrically coupled with the base;
a self-aligned dielectric sidewall spacer disposed between the base contact and the emitter, wherein the base contact is self-aligned relative to the self-aligned dielectric sidewall spacer and a predetermined base-to-emitter spacing is provided thereby; and
a self-aligned base mesa being aligned relative to the self-aligned base contact; and
a base metal contact pad overlaying a portion of the emitter, the base metal contact pad electrically coupled with the base contact.
15. A heterojunction bipolar transistor comprising:
a base contact self-alignedly disposed upon and electrically coupled with a base;
a dielectric sidewall spacer with a predetermined spacer thickness self-alignedly disposed between the base contact and an emitter;
a self-aligned base mesa defined by the self-aligned base contact; and
a base metal contact pad on the base mesa, the base metal contact pad contacting the dielectric sidewall spacer.
16. The heterojunction bipolar transistor of claim 15 including:
a p-type InGaAs material in the base; and
an n-type InP material in the emitter.
17. A transistor comprising:
a collector;
a base overlaying at least a portion of the collector;
an emitter overlying at least a portion of the base;
a base metal contact pad overlaying at least part of a portion of the emitter, the base metal contact pad electrically coupled to the base by a base ohmic contact, the base ohmic contact being a self-aligned base contact sidewall spacer; and
a self-aligned base mesa defined by the base contact sidewall spacer.
18. A transistor comprising:
a collector;
a base overlaying at least a portion of the collector;
an emitter overlying at least a portion of the base;
a base metal contact pad overlaying at least part of a portion of the emitter, the base metal contact pad electrically coupled to the base by a base contact sidewall; and
a dielectric sidewall spacer, the dielectric sidewall spacer being between the base contact sidewall and the emitter.
19. The transistor of claim 18 further comprising an emitter oxide, the emitter oxide being between the base metal contact pad and the emitter.