IP Library Granted Patent US 8,253,395
Granted Patent B2
US 8,253,395 · App. 12/536,596 · Granted Aug 28, 2012

Bus voltage optimizer for switched power converter

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,253,395
App. No.
12/536,596
Granted
Aug 28, 2012
Kind
B2
Abstract

Methods, systems, and devices are provided for optimizing a bus voltage supplied to a switching power converter to keep the duty cycle of the switching power converter to within a desirable operating range. In some embodiments, the duty cycle of the switching signal used to drive the switching power converter is monitored (e.g., indirectly) to determine whether the duty cycle is approaching an undesirable level. For example, as the duty cycle decreases (e.g., approaches or crosses a certain threshold), embodiments decrease the bus voltage. This may, in turn, allow the switching power converter to output substantially the same output to the load, while using a more efficient (e.g., larger) duty cycle. Certain embodiments use similar techniques, along with certain bus voltage optimization techniques, to control a bus voltage as a function of feedback from multiple switching power converters.

Claims (70)

1. A circuit comprising:

a converter controller unit, operable to:

generate an output error as a function of monitoring an output level of a converter unit with respect to a target output level; and

control a duty cycle of a switching signal as a function of the output error; and

a bus controller unit, communicatively coupled with the converter controller unit, and operable to:

generate a bus control signal as a function of the duty cycle of the switching signal; and

adjust a bus voltage level as a function of the bus control signal such that the duty cycle of the switching signal is maintained substantially within a predefined operational range.

2. The circuit recited in claim 1 ,

wherein the bus controller unit is operable to generate the bus control signal as a function of the duty cycle of the switching signal by comparing the output error generated by the converter controller unit against a threshold output error level.

3. The circuit recited in claim 1 ,

wherein the bus controller unit is operable to decrease the bus voltage level when the duty cycle of the switching signal approaches a threshold minimum duty cycle.

4. The circuit recited in claim 1 ,

wherein the bus controller unit is operable to increase the bus voltage level when the duty cycle of the switching signal approaches a threshold maximum duty cycle.

5. The circuit recited in claim 1 , wherein the converter controller unit comprises:

a sampling unit, operable to monitor the output level of the converter unit by sampling a representative level at a representative portion of each cycle of the switching signal, the representative level being functionally related to the output level;

an output error generator unit, communicatively coupled with the sampling unit, and operable to generate the output error by comparing the sampled representative level against a reference level; and

a switching signal generator unit, communicatively coupled with the output error generator unit, and operable to generate the switching signal as a function of comparing the output error against a reference periodic signal.

6. The circuit recited in claim 1 , wherein:

the converter controller unit comprises a switching signal generator unit, operable to generate the switching signal as a function of comparing the output error against a reference periodic signal, the reference periodic signal being generated as a function of a maximum threshold level; and

the bus controller unit comprises a bus control signal generator unit operable to generate the bus control signal as a function of the duty cycle of the switching signal by comparing the output error against the maximum threshold level.

7. The circuit recited in claim 6 , wherein:

the bus control signal generator unit comprises a difference amplifier configured to:

receive the output error at a first input node;

receive the maximum threshold level at a second input node; and

generate the bus control signal at an output node, such that the bus control signal is functionally related to a difference between the output error and the maximum threshold level.

8. The circuit recited in claim 6 , wherein:

the bus control signal generator unit comprises loop compensation components.

9. The circuit recited in claim 1 , wherein:

an operational efficiency of the converter unit is functionally related to the duty cycle of the switching signal; and

the operational range of the duty cycle of the switching signal is determined to optimize the operational efficiency of the converter unit.

10. The circuit recited in claim 1 , further comprising:

the converter unit, operable to generate the output level as a function of the duty cycle of the switching signal and the bus voltage level.

11. The circuit recited in claim 10 ,

wherein the converter unit is configured as a low-side switch.

12. A switched mode power supply comprising the circuit recited in claim 1 .

13. A method for controlling a switching power converter, the method comprising:

monitoring an output level of a converter unit with respect to a target output level, the converter unit being configured to generate an output level as a function of a duty cycle of a switching signal and a bus voltage level;

generating an output error as a function of monitoring the output level;

controlling the duty cycle of the switching signal as a function of the output error;

generating a bus control signal as a function of the output error; and

adjusting the bus voltage level as a function of the bus control signal such that the duty cycle of the switching signal is maintained substantially within a predefined operational range.

14. The method recited in claim 13 , wherein generating the bus control signal as a function of the output error comprises:

comparing the output error against a threshold output error level.

15. The method recited in claim 13 , wherein adjusting the bus voltage level as a function of the bus control signal such that the duty cycle of the switching signal is maintained substantially within a predefined operational range comprises:

increasing the bus voltage level when the duty cycle of the switching signal approaches a maximum region of the predefined operational range.

16. The method recited in claim 13 , wherein generating the output error comprises:

comparing a sampled representative level against a reference level, wherein monitoring the output level of the converter unit comprises sampling a representative level at a representative portion of each cycle of the switching signal to generate the sampled representative level, the sampled representative level being functionally related to the output level.

17. The method recited in claim 13 , further comprising:

generating the switching signal as a function of comparing the output error against a reference periodic signal.

18. The method recited in claim 17 , further comprising:

generating the bus control signal as a function of the duty cycle of the switching signal by comparing the output error against a maximum threshold level, wherein the reference periodic signal is generated as a function of the maximum threshold level.

19. The method recited in claim 18 , wherein generating the bus control signal as a function of the duty cycle comprises calculating a difference between the output error and the maximum threshold level.

20. A circuit comprising:

an optimizer unit, communicatively coupled with a plurality of bus controller units, and operable to:

receive a plurality of bus control signals, each bus control signal being generated by a respective one of the plurality of bus controller units as a function of a duty cycle of a switching signal adapted for use in driving at least one of a plurality of switching converter units communicatively coupled with the respective one of the plurality of bus controller units;

generate a bus optimizer signal as a function of the plurality of bus control signals; and

adjust a bus voltage level as a function of the bus optimizer signal, the bus voltage level being tied to the plurality of switching converter units, such that the duty cycles of the switching signals are maintained substantially within respective predefined operational ranges.

21. The circuit recited in claim 20 , wherein the optimizer unit comprises:

a voting circuit, operable to select one of the plurality of bus control signals as a selected control signal, wherein the bus optimizer signal is generated as a function of the selected control signal.

22. The circuit recited in claim 21 ,

wherein the voting circuit is operable to select the one of the plurality of bus control signals having a smallest amplitude as the selected control signal.

23. The circuit recited in claim 20 , wherein each of the plurality of bus controller units is communicatively coupled with a converter controller unit operable to:

generate an output error as a function of monitoring an output level of at least one of a plurality of switching converter units communicatively coupled with the respective one of the plurality of bus controller units with respect to a target output level; and

control the duty cycle of the switching signal as a function of the output error.

24. A method for controlling a plurality of switching power converters comprising:

receiving a plurality of bus control signals, each bus control signal being generated by a respective one of the plurality of bus controller units as a function of a duty cycle of a switching signal adapted for use in driving at least one of a plurality of switching converter units communicatively coupled with the respective one of the plurality of bus controller units;

generating a bus optimizer signal as a function of the plurality of bus control signals; and

adjusting a bus voltage level as a function of the bus optimizer signal, the bus voltage level being tied to the plurality of switching converter units, such that the duty cycles of the switching signals are maintained substantially within respective predefined operational ranges.

25. The method recited in claim 24 , further comprising:

selecting one of the plurality of bus control signals as a selected control signal, wherein the bus optimizer signal is generated as a function of the selected control signal.

Assignments (19)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
NOTICE OF SUCCESSION OF AGENCY Recorded Apr 9, 2015
From: ROYAL BANK OF CANADA (AS SUCCESSOR TO MORGAN STANLEY & CO. LLC)
To: BANK OF AMERICA, N.A., AS SUCCESSOR AGENT
Reel/Frame 035657/0223 →
SUPPLEMENTAL PATENT SECURITY AGREEMENT Recorded Nov 11, 2011
From: MICROSEMI CORPORATION; MICROSEMI CORP. - ANALOG MIXED SIGNAL GROUP; MICROSEMI CORP. - MASSACHUSETTS; ACTEL CORPORATION
To: MORGAN STANLEY & CO. LLC
Reel/Frame 027213/0611 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2011
From: ASIC ADVANTAGE INC.
To: MICROSEMI CORPORATION
Reel/Frame 027096/0222 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2009
From: IRISSOU, PIERRE; COLMET-DAAGE, ETIENNE
To: ASIC ADVANTAGE INC.
Reel/Frame 023118/0229 →