Integrated circuit packaging system with laser hole and method of manufacture thereof

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

molding a first encapsulation above the substrate;

forming a via through the first encapsulation;

mounting an integrated circuit above the substrate and between sides of the first encapsulation;

forming a second encapsulation covering the integrated circuit and the first encapsulation; and

connecting an external package to the substrate through the via.

2. The method as claimed in claim 1 further comprising connecting a second integrated circuit above the first integrated circuit and directly connected to the via with an interconnect.

3. The method as claimed in claim 1 wherein encapsulating the integrated circuit includes forming an exterior surface coplanar with the first encapsulation and coplanar with the substrate.

4. The method as claimed in claim 1 wherein forming the via includes forming the via coplanar with a planar surface of the first encapsulation.

5. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

molding a first encapsulation above the substrate and along a perimeter region of the substrate;

forming a first via through the first encapsulation;

mounting an integrated circuit between sides of the first encapsulation above the substrate and directly connected to the substrate with an interconnect;

forming a second encapsulation covering the integrated circuit and the first encapsulation; and

forming a second via through the second encapsulation from the first via and exposed from a top surface of the second encapsulation.

6. The method as claimed in claim 5 wherein forming the first via includes forming the first via having a pillar, a paste, and a spheroid.

7. The method as claimed in claim 5 wherein forming the first via includes forming the first via having a vertical conductor.

8. The method as claimed in claim 5 wherein encapsulating the integrated circuit includes forming the top surface having a depression.

9. The method as claimed in claim 5 wherein forming the second via includes forming the second via coplanar with the top surface of the second encapsulation.

10. An integrated circuit packaging system comprising:

a substrate;

a first encapsulation molded above the substrate, wherein the first encapsulation is formed along a perimeter region of the substrate;

a first via formed through the first encapsulation;

an integrated circuit mounted above the substrate and between sides of the first encapsulation, wherein the integrated circuit is directly connected to the substrate with an interconnect;

a second encapsulation covering the integrated circuit and the first encapsulation; and

a second via formed through the second encapsulation from the first via and exposed from a top surface of the second encapsulation.

11. The system as claimed in claim 10 further comprising a second integrated circuit mounted above the first integrated circuit and directly connected to the via with an interconnect.

12. The system as claimed in claim 10 further comprising an external package connected to the substrate through the via.

13. The system as claimed in claim 10 further comprising an exterior surface of the second encapsulation coplanar with the first encapsulation and coplanar with the substrate.

14. The system as claimed in claim 10 wherein the via is formed coplanar with a planar surface of the first encapsulation.

15. The system as claimed in claim 10 wherein the first via has a pillar, a paste, and a spheroid.

16. The system as claimed in claim 10 wherein the first via has a vertical conductor.

17. The system as claimed in claim 10 wherein the top surface has a depression.

18. The system as claimed in claim 10 wherein the second via is formed coplanar with the top surface of the second encapsulation.