IP Library › Granted Patent US 9,118,281
Granted Patent B2
US 9,118,281 · App. 13/897,192 · Granted Aug 25, 2015

Integrated start-up bias boost for dynamic error vector magnitude enhancement

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Quick Facts
Patent No.
US 9,118,281
App. No.
13/897,192
Granted
Aug 25, 2015
Kind
B2
Abstract

Devices and methods for correcting for start-up transients in integrated power amplifiers are disclosed. A delay element is arranged to produce a delay waveform signal that is responsive to an input voltage signal. A transconductance element has an input that receives the delay waveform signal and is arranged to provide an output boost current that is based on the delay waveform signal and a gain of the transconductance element. A reference element provides an output bias current that is responsive to a static reference current and the boost current. A bias element has an input that receives the bias current and is arranged to provide a bias control output. A power amplifier is responsive to the bias control output and is arranged to provide an amplified power output. In some examples, the boost current is adjusted based on a supply voltage and an input power of the power amplifier.

Claims (50)

1. A circuit that corrects for start-up transients in power amplifiers, comprising:

a boost generator arranged to provide a boost current;

a reference element that provides an output bias current responsive to a static reference current and the boost current;

a bias element having an input that receives the bias current and is arranged to provide a bias control output;

a power amplifier responsive to the bias control output and arranged to provide an amplified power output, wherein the power amplifier provides a first amount of power gain during a first time period after the power amplifier is powered on, the first amount of power gain responsive to the sum of the boost current and the static reference current and a second amount of power gain during a second time period after the power amplifier is powered on, the second time period following the first time period, the second amount of power gain determined by decay of the output bias current to a value of the static reference current; and

a polarity inversion circuit having an input that receives the boost current and is arranged to provide an output that is a mirrored boost current, wherein the bias current is responsive to the mirrored boost current.

2. The circuit of claim 1 , wherein the output bias current is the sum of the static reference current and the mirrored boost current.

3. A circuit that corrects for start-up transients in power amplifiers, comprising:

a boost generator arranged to provide a boost current, the boost generator includes a delay element and a transconductance element and wherein the delay element includes a capacitor and a first resistor, a second resistor, and a third resistor that are electrically coupled together in series and are digitally controllable;

a reference element that provides an output bias current responsive to a static reference current and the boost current;

a bias element having an input that receives the bias current and is arranged to provide a bias control output; and

a power amplifier responsive to the bias control output and arranged to provide an amplified power output, wherein the power amplifier provides a first amount of power gain during a first time period after the power amplifier is powered on, the first amount of power gain responsive to the sum of the boost current and the static reference current and a second amount of power gain during a second time period after the power amplifier is powered on, the second time period following the first time period, the second amount of power gain determined by decay of the output bias current to a value of the static reference current.

4. A circuit that corrects for start-up transients in power amplifiers, comprising:

a boost generator arranged to provide a boost current, the boost generator includes a delay element and a transconductance element, the transconductance element includes a switch and at least one resistor electrically coupled together in series;

a reference element that provides an output bias current responsive to a static reference current and the boost current;

a bias element having an input that receives the bias current and is arranged to provide a bias control output;

a power amplifier responsive to the bias control output and arranged to provide an amplified power output, wherein the power amplifier provides a first amount of power gain during a first time period after the power amplifier is powered on, the first amount of power gain responsive to the sum of the boost current and the static reference current and a second amount of power gain during a second time period after the power amplifier is powered on, the second time period following the first time period, the second amount of power gain determined by decay of the output bias current to a value of the static reference current.

5. A circuit that corrects for start-up transients in power amplifiers, comprising:

a boost generator arranged to provide a boost current, the boost generator includes a delay element and a transconductance element, the delay element is arranged to produce a delay waveform signal responsive to an input voltage signal and the transconductance element has an input that receives the delay waveform signal from the delay element and is arranged to provide the output boost current, the output of the transconductance element is adjusted by a scaling factor that is based on a supply voltage of the power amplifier, wherein the transconductance element includes a first resistor, a second resistor, and a third resistor that are electrically coupled together in series and are digitally controllable;

a reference element that provides an output bias current responsive to a static reference current and the boost current;

a bias element having an input that receives the bias current and is arranged to provide a bias control output; and

a power amplifier responsive to the bias control output and arranged to provide an amplified power output, wherein the power amplifier provides a first amount of power gain during a first time period after the power amplifier is powered on, the first amount of power gain responsive to the sum of the boost current and the static reference current and a second amount of power gain during a second time period after the power amplifier is powered on, the second time period following the first time period, the second amount of power gain determined by decay of the output bias current to a value of the static reference current.

6. A circuit that corrects for start-up transients in power amplifiers, comprising:

a boost generator arranged to provide a boost current, the boost generator includes a delay element and a transconductance element, the delay element is arranged to produce a delay waveform signal responsive to an input voltage signal and the transconductance element has an input that receives the delay waveform signal from the delay element and is arranged to provide the output boost current, the output of the transconductance element is adjusted by a scaling factor that is based on a supply voltage of the power amplifier;

a reference element that provides an output bias current responsive to a static reference current and the boost current;

a bias element having an input that receives the bias current and is arranged to provide a bias control output;

a power amplifier responsive to the bias control output and arranged to provide an amplified power output, wherein the power amplifier provides a first amount of power gain during a first time period after the power amplifier is powered on, the first amount of power gain responsive to the sum of the boost current and the static reference current and a second amount of power gain during a second time period after the power amplifier is powered on, the second time period following the first time period, the second amount of power gain determined by decay of the output bias current to a value of the static reference current; and

a power scaling element that adjusts the boost current by a power scaling factor that is based on the output power of the power amplifier.

7. The circuit of claim 6 , wherein the power scaling factor is proportional to the magnitude of the output power of the power amplifier.

8. The circuit of claim 6 , wherein the power scaling factor is proportional to the magnitude of the output power of the power amplifier.

9. A method of correcting for a start-up transient in a power amplifier, comprising:

producing a boost current having a decay characteristic;

producing a static reference current;

adjusting the boost current by a scaling factor that is based on a supply voltage of the power amplifier and an input power of the power amplifier;

summing the boost current and the static reference current;

applying the summed boost current and the static reference current to bias a power amplifier;

wherein the boost current is produced by a delay element having an input that receives an enabling control signal and is arranged to provide an output that includes a delay output signal and a transconductance element having an input that receives the delay output voltage from the delay element and is arranged to provide an output that includes the boost current that is based on the delay output voltage and a gain of the transconductance element, wherein the delay element includes a switch and at least one resistor coupled together in series.

10. A method of correcting for a start-up transient in a power amplifier, comprising:

producing a boost current having a decay characteristic;

producing a static reference current;

adjusting the boost current by a scaling factor that is based on a supply voltage of the power amplifier and an input power of the power amplifier;

summing the boost current and the static reference current;

applying the summed boost current and the static reference current to bias a power amplifier;

wherein the boost current is produced by a delay element having an input that receives an enabling control signal and is arranged to provide an output that includes a delay output signal and a transconductance element having an input that receives the delay output voltage from the delay element and is arranged to provide an output that includes the boost current that is based on the delay output voltage and a gain of the transconductance element, wherein the transconductance element includes a switch and at least one resistor coupled together in series.

11. A method of correcting for a start-up transient in a power amplifier, comprising:

producing a boost current having a decay characteristic;

producing a static reference current;

adjusting the boost current by a scaling factor that is based on a supply voltage of the power amplifier and an input power of the power amplifier, wherein the scaling factor is a voltage scaling factor that is proportional to the supply voltage and a power scaling factor that is proportional to the magnitude of an output power to the power amplifier;

summing the boost current and the static reference current;

applying the summed boost current and the static reference current to bias a power amplifier.

Assignments (18)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2025
From: MICROCHIP TECHNOLOGY INC.; MICROCHIP TECHNOLOGY IRELAND LIMITED; MICROSEMI CORPORATION; ATMEL CORPORATION; SILICON STORAGE TECHNOLOGY, INC.; MICROSEMI FREQUENCY AND TIME CORP.; MICROSEMI SEMICONDUCTOR ULC; MICROCHIP TECHNOLOGY GERMANY GMBH
To: CRESTONE IP MANAGEMENT, LLC
Reel/Frame 071991/0419 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
SECURITY AGREEMENT Recorded Apr 22, 2015
From: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP; MICROSEMI SEMICONDUCTOR (U.S.) INC.; MICROSEMI SOC CORP.; MICROSEMI FREQUENCY AND TIME CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 3, 2013
From: HERSHBERGER, KYLE; EPLETT, BRIAN; SANTINI, MARK
To: MICROSEMI CORPORATION
Reel/Frame 030738/0426 →