Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.
1. A method of making a semiconductor device, comprising:
providing a substrate including a plurality of trace lines;
forming a mask patch between the trace lines; and
disposing an interconnect structure over one of the trace lines.
2. The method of claim 1 , wherein:
the trace lines include integrated bump pads that are co-linear with the trace lines; and
the mask patch is formed between the integrated bump pads.
3. The method of claim 1 , further including disposing a semiconductor die over the substrate.
4. The method of claim 1 , wherein the mask patch is isolated and formed within an array of integrated bump pads on the trace lines.
5. The method of claim 1 , wherein the interconnect structure includes a non-fusible portion and fusible portion.
6. The method of claim 1 , wherein the mask patch confines the interconnect structure on one of the trace lines.
7. A method of making a semiconductor device, comprising:
providing a substrate including a plurality of trace lines comprising integrated bump pads; and
forming a plurality of isolated mask patches between the integrated bump pads.
8. The method of claim 7 , further including disposing a semiconductor die over the substrate.
9. The method of claim 7 , further including disposing an interconnect structure over one of the integrated bump pads.
10. The method of claim 9 , wherein the interconnect structure includes a non-fusible portion and fusible portion.
11. The method of claim 7 , further including forming the isolated mask patches interstitially within an array of the integrated bump pads.
12. The method of claim 7 , wherein:
the integrated bump pads are co-linear with the trace lines; and
the isolated mask patches are formed between the integrated bump pads.
13. The method of claim 9 , wherein the isolated mask patches confine the interconnect structure around the integrated bump pads.
14. A method of making a semiconductor device, comprising:
providing a substrate including a plurality of trace lines comprising integrated bump pads; and
forming a plurality of isolated mask patches around the integrated bump pads.
15. The method of claim 14 , further including disposing a semiconductor die over the substrate.
16. The method of claim 14 , further including forming an interconnect structure over an integrated bump pad from the integrated bump pads.
17. The method of claim 16 , wherein forming the interconnect structure includes forming a fusible portion and a non-fusible portion.
18. The method of claim 14 , further including forming the isolated mask patches interstitially within an array of the integrated bump pads.
19. The method of claim 18 , further including:
forming the integrated bump pads co-linear with the trace lines; and
forming the mask patches between the integrated bump pads.
20. A method of making a semiconductor device, comprising:
providing a substrate including a plurality of trace lines; and
forming a plurality of mask patches between trace lines.
21. The method of claim 20 , further including disposing a semiconductor die over the substrate.
22. The method of claim 20 , further including forming an interconnect structure over the plurality of trace lines.
23. The method of claim 22 , wherein forming the interconnect structure further includes forming a non-fusible portion and fusible portion.
24. The method of claim 20 , further including forming the mask patches interstitially within an array of integrated bump pads on the trace lines.
25. The method of claim 24 , further including:
forming the integrated bump pads co-linear with the trace lines; and
forming the mask patches between the integrated bump pads.