IP Library Granted Patent US 9,136,802
Granted Patent B2
US 9,136,802 · App. 14/090,401 · Granted Sep 15, 2015

Integrated start-up bias boost for dynamic error vector magnitude enhancement

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Quick Facts
Patent No.
US 9,136,802
App. No.
14/090,401
Granted
Sep 15, 2015
Kind
B2
Abstract

Devices and methods for correcting for start-up transients in integrated power amplifier are disclosed. A power amplifier is responsive to a bias control output and is arranged to provide an amplified power output. In some examples, the boost current is adjusted based on a supply voltage and an input power of the power amplifier. The power amplifier can operate in a low power and a high power mode and the adjustments can be made to the supply voltage and/or the input power vary depending on whether the power amplifier is operating in the high or low power mode. The adjustments for the high power mode operation are different than and correspond to the high power mode input power and voltage and the adjustments for the low power mode operation are different than and correspond to the low power mode input power and voltage.

Claims (35)

1. A method for correcting for a start-up transient in a power amplifier in a wireless local area network device, the power amplifier being operational at a high power level and a low power level, comprising:

in response to receiving a control signal that indicates that the power amplifier is to operate at the high power level, operating the power amplifier at the high power level;

in response to receiving a control signal that indicates that the power amplifier is to operate at the low power level, operating the power amplifier at the low power level by:

sending an instruction to a supply voltage regulator to apply a low supply voltage to the power amplifier;

producing a low power level boost current having a low power level decay characteristic;

producing a low power level static reference current;

adjusting the low power level boost current by a low power level scaling factor;

summing the low power level boost current and the low power level static reference current; and

applying the summed low power level boost current and the low power level static reference current to bias the power amplifier for the low power level.

2. The method of claim 1 , wherein operating the power amplifier at the high power level includes:

producing a high power level boost current having a high power level decay characteristic;

producing a high power level static reference current;

adjusting the high power level boost current by a high power level scaling factor;

summing the high power level boost current and the high power level static reference current; and

applying the summed high power level boost current and the high power level static reference current to bias the power amplifier for the high power level.

3. The method of claim 1 , wherein when the power amplifier operates at the low power level, the power amplifier provides a first amount of power gain during a first time period after the power amplifier is powered on, the first amount of power gain responsive to the sum of the low power level boost current and the low power level static reference current and a second amount of power gain during a second time period after the power amplifier is powered on, the second time period following the first time period, the second amount of power gain determined by decay of the summed low power level boost current to a value of the low power level static reference current.

4. The method of claim 3 , wherein the decay of the low power level boost current begins when the control signal indicating that the power amplifier is to operate at the low power level is supplied to the power amplifier.

5. The method of claim 1 , wherein the low power level scaling factor includes a low power level voltage scaling factor that adjusts the low power level supply voltage and a low power level power scaling factor that adjusts a low power level input power supplied to the power amplifier.

6. The method of claim 1 , wherein when the power amplifier operates at the high power level, the power amplifier provides a first amount of power gain during a first time period after the power amplifier is powered on, the first amount of power gain responsive to the sum of the high power level boost current and the high power level static reference current and a second amount of power gain during a second time period after the power amplifier is powered on, the second time period following the first time period, the second amount of power gain determined by decay of the summed high power level boost current to a value of the high power level static reference current.

7. The method of claim 6 , wherein the decay of the high power level boost current begins when the control signal indicating that the power amplifier is to operate at the high power level is supplied to the power amplifier.

8. The method of claim 1 , wherein the high power level scaling factor includes a high power level voltage scaling factor that adjusts the high power level supply voltage and a high power level power scaling factor that adjusts a high power level input power supplied to the power amplifier.

9. The method of claim 1 , wherein operating the power amplifier at the high power level includes applying a high power level supply voltage to the power amplifier.

10. The method of claim 1 , wherein operating the power amplifier at the high power level includes instructing the supply voltage regulator to apply a high power level supply voltage to the power amplifier.

11. The method of claim 10 , wherein operating the power amplifier at the low power level includes sending an instruction to the supply voltage regulator to reduce the supply voltage from the high power level supply voltage to the low power level supply voltage.

12. The method of claim 1 , further comprising receiving the control signal that indicates that the power amplifier is to operate at the low power level at a control pin of a baseband radio that is dedicated to instructing the power amplifier to operate at the low power level.

13. A circuit that corrects for start-up transients in a power amplifier in a wireless local area network device, the power amplifier operational at a high power level and a low power level, the circuit comprising:

a control signal receiving element arranged to receive a control signal from a baseband radio of the wireless local area network device and arranged to determine if the control signal includes a high power level enabling signal having a high power level supply voltage or a low power level enabling signal having a low power level supply voltage;

a supply voltage regulator arranged to be set to a high power level supply voltage if the control signal includes the high power level enabling signal and also arranged to be set to a low power level supply voltage if the control signal includes the lower power level enabling signal;

a boost generator arranged to provide a high power level output boost current if the control signal receiving element determines that the control signal includes a high power level enabling signal and to provide a low power level output boost current if the control signal receiving element determines that the control signal includes a low power level enabling signal;

a bias element having an input that is arranged to receive the high power level boost current or the low power level boost current from the boost generator, the bias element arranged to provide a high power level boost control output in response to receiving the high power level boost current or to provide a low power level boost control output in response to receiving the low power level boost current; and

a power amplifier responsive to high power level supply voltage and the high power level boost control output, the power amplifier also responsive to the low power level supply voltage and the low power level boost control output from the bias element, the power amplifier arranged to provide an amplified high power level power output if the high power level boost control output is applied to the power amplifier and an amplified low power level power output if the low power level boost control output is applied to the power amplifier,

wherein the power amplifier:

in response to the high power level boost control output, provides a high power level first amount of power gain during a first time period after the power amplifier is powered on with the high power level enabling signal, the high power level first amount of power gain responsive to the sum of the high power level boost current and the high power level static reference current, and a high power level second amount of power gain during a second time period after the power amplifier is powered on, the high power level second time period following the first time period, the high power level second amount of power gain

determined by decay of the high power level output bias current to a value of the high power level static reference current; and

in response to the low power level boost control output, provides a low power level first amount of power gain during a first time period after the power amplifier is powered on with the low power level enabling signal, the first amount of power gain responsive to the sum of the low power level boost current and the low power level static reference current, and a low power level second amount of power gain during a second time period after the power amplifier is powered on, the second time period following the first time period, the low power level second amount of power gain determined by decay of the low power level output bias current to a value of the low power level static reference current.

Assignments (18)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2025
From: MICROCHIP TECHNOLOGY INC.; MICROCHIP TECHNOLOGY IRELAND LIMITED; MICROSEMI CORPORATION; ATMEL CORPORATION; SILICON STORAGE TECHNOLOGY, INC.; MICROSEMI FREQUENCY AND TIME CORP.; MICROSEMI SEMICONDUCTOR ULC; MICROCHIP TECHNOLOGY GERMANY GMBH
To: CRESTONE IP MANAGEMENT, LLC
Reel/Frame 071991/0419 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
SECURITY AGREEMENT Recorded Apr 22, 2015
From: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP; MICROSEMI SEMICONDUCTOR (U.S.) INC.; MICROSEMI SOC CORP.; MICROSEMI FREQUENCY AND TIME CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 035477/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2013
From: POULIN, DARCY; HERSHBERGER, KYLE; EPLETT, BRIAN; SANTINI, MARK
To: MICROSEMI CORPORATION
Reel/Frame 031679/0298 →