Voidlessly encapsulated semiconductor die package

1. A system, comprising:

a semiconductor die having a first side and a second side opposite the first side;

a first slug coupled to a portion of the first side of the die;

a second slug coupled to a portion of the second side of the die; and

an insulating material voidlessly encapsulating the die,

wherein the first slug includes a first portion having a first width in proximity to the die and a second portion having a second width, wherein the first portion is closer than the second portion to the die and the first width is smaller than the second width, and

wherein the semiconductor die comprises a silicon carbide die.

2. The system of claim 1 , wherein the first portion comprises a truncated cone.

3. The system of claim 2 , wherein the slope of the cone is approximately N degrees off an axis of the cone and N comprises a value between 10 degrees and 80 degrees.

4. The system of claim 3 , wherein the slope of the cone is approximately 45 degrees off the axis of the cone.

5. The system of claim 1 , wherein the first portion comprises a cylinder having a smaller width than the second portion.

6. The system of claim 1 , wherein the first portion varies from the first width to the second width to form one of a convex surface, a concave-convex surface, and a concave surface.

7. The system of claim 1 , wherein the semiconductor die comprises a planar die.

8. The system of claim 1 , wherein the first slug comprises one of molybdenum and tungsten.

9. The system of claim 1 , wherein the shape and size of the second slug is substantially identical to the shape and size of the first slug.

10. The system of claim 1 , wherein the semiconductor die has a width approximately equal to the second width.

11. The system of claim 10 , wherein, when the semiconductor die includes a cross section that is one of a square or a hexagon, the semiconductor die has a major diagonal approximately equal to the second width.

12. The system of claim 10 , wherein, when the first slug is cylindrical, the first width corresponds to a first diameter of the slug and the second width corresponds to a second diameter of the slug.

13. The system of claim 1 , wherein the semiconductor die includes a passivation layer in an area corresponding to a difference between the second width and the first width.

14. The system of claim 1 , wherein the insulating material comprises a high dielectric strength glass.

15. The system of claim 1 , wherein the first width corresponds to a metallization area on a surface of the semiconductor die.

16. The system of claim 1 , wherein the first slug is provided with one of a lead or a surface mount connector.

17. A system, comprising:

a semiconductor die having a first side and a second side opposite the first side;

a first slug coupled to a portion of the first side of the die;

a second slug coupled to a portion of the second side of the die;

a second semiconductor die located adjacent to the semiconductor die; and

an insulating material voidlessly encapsulating the die,

wherein the first slug includes a first portion having a first width in proximity to the die and a second portion having a second width, wherein the first portion is closer than the second portion to the die and the first width is smaller than the second width.

18. The system of claim 17 , wherein the second semiconductor die is arranged between the semiconductor die and the second slug.

19. The system of claim 17 , wherein the second semiconductor die is arranged back-to-back with the semiconductor die and wherein both the first slug and the second slug are tapered.

20. A system, comprising:

a semiconductor die having a first side and a second side opposite the first side;

a first slug coupled to a portion of the first side of the die;

a second slug coupled to a portion of the second side of the die;

a second semiconductor die located between the second slug and a third slug; and

an insulating material voidlessly encapsulating the die,

wherein the first slug includes a first portion having a first width in proximity to the die and a second portion having a second width, wherein the first portion is closer than the second portion to the die and the first width is smaller than the second width.

21. The system of claim 20 , further comprising a third semiconductor die located between the third slug and a fourth slug.

22. A printed circuit board comprising the system of claim claim 1 .

23. A power supply comprising the system of claim 1 .

24. A satellite system comprising the system of claim 1 .

25. A method of manufacture, comprising:

coupling a first slug to a portion of a first side of a semiconductor die having the first side and a second side opposite the first side;

coupling a second slug to a portion of the second side; and

voidlessly encapsulating the die with an insulating material;

wherein the first slug includes a first portion having a first width in proximity to the die and a second portion having a second width, wherein the first portion is closer than the second portion to the die and the first width is smaller than the second width, and

wherein the semiconductor die comprises a silicon carbide die.

26. The method of claim 25 , wherein the first portion comprises a truncated cone.

27. The method of claim 25 , wherein the semiconductor die comprises a planar die.

28. The method of claim 25 , wherein the first slug comprises one of molybdenum and tungsten.

29. The method of claim 25 , wherein the shape and size of the second slug is substantially identical to the shape and size of the first slug.

30. The method of claim 25 , wherein the semiconductor die has a width approximately equal to the second width.

31. The method of claim 25 , wherein the semiconductor die includes a passivation layer in an area corresponding to a difference between the second width and the first width.

32. The method of claim 25 , wherein the insulating material comprises a high dielectric strength glass.

33. The method of claim 25 , wherein the first width corresponds to a metallization area on a surface of the semiconductor die.

34. The method of claim 25 , wherein the first slug is provided with one of a lead or a surface mount connector.

35. The method of claim 25 , further comprising installing the semiconductor die, the first slug, and the second slug on a printed circuit board.

36. The method of claim 25 , further comprising installing the semiconductor die, the first slug, and the second slug in a power supply.

37. The method of claim 25 , further comprising installing the semiconductor die, the first slug, and the second slug in a satellite system.

38. A method of manufacture, comprising:

coupling a first slug to a portion of a first side of a semiconductor die having the first side and a second side opposite the first side;

coupling a second slug to a portion of the second side;

coupling a second semiconductor die between the second slug and a third slug; and

voidlessly encapsulating the die with an insulating material;

wherein the first slug includes a first portion having a first width in proximity to the die and a second portion having a second width, wherein the first portion is closer than the second portion to the die and the first width is smaller than the second width.

39. A method of manufacture, comprising:

coupling a first slug to a portion of a first side of a semiconductor die having the first side and a second side opposite the first side;

coupling a second slug to a portion of the second side;

coupling a second semiconductor die adjacent to the semiconductor die; and

voidlessly encapsulating the die with an insulating material;

wherein the first slug includes a first portion having a first width in proximity to the die and a second portion having a second width, wherein the first portion is closer than the second portion to the die and the first width is smaller than the second width.

40. The method of claim 39 , wherein the second semiconductor die is arranged between the semiconductor die and the second slug.

41. The method of claim 39 , wherein the second semiconductor die is arranged back-to-back with the semiconductor die and wherein both the first slug and the second slug are tapered.

42. The method of claim 38 , further comprising coupling a third semiconductor die between the third slug and a fourth slug.