3D semiconductor device and structure
A 3D semiconductor device, the device including: a first layer including first transistors each including a silicon channel; a second layer including second transistors each including a silicon channel, the second layer overlaying the first transistors, where at least one of the second transistors is at least partially self-aligned to at least one of the first transistors; and a third layer including third transistors each including a single crystal silicon channel, the third layer underlying the first transistors, where a plurality of the third transistors form a logic circuit, and where the logic circuit is aligned to the second transistors with less than 200 nm alignment error, where the first layer thickness is less than one micron, and where the first transistor is a junction-less transistor.
1. A 3D semiconductor device, the device comprising:
a first layer comprising first transistors each comprising a silicon channel;
a second layer comprising second transistors each comprising a silicon channel, said second layer overlaying said first transistors,
wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and
a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer underlying said first transistors,
wherein a plurality of said third transistors form a logic circuit, and
wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error,
wherein said first layer thickness is less than one micron, and
wherein said first transistors are junction-less transistors.
2. The 3D semiconductor device according to claim 1 ,
wherein said second transistors comprise a polysilicon channel.
3. The 3D semiconductor device according to claim 1 ,
wherein said first layer comprises a non-volatile memory cell.
4. The 3D semiconductor device according to claim 1 ,
wherein said first layer comprises side-gate transistors.
5. The 3D semiconductor device according to claim 1 ,
wherein said self-aligned is a visible result of at least two vertically stacked structures being processed together following a single lithography step.
6. The 3D semiconductor device according to claim 1 , further comprising:
periphery circuits,
wherein said periphery circuits comprise said logic circuit.
7. The 3D semiconductor device according to claim 1 ,
wherein at least one of said first transistors are directly connected to at least one of said second transistors.
8. A 3D semiconductor device, the device comprising:
a first layer comprising first transistors each comprising a silicon channel;
a second layer comprising second transistors each comprising a silicon channel, said second layer overlaying said first transistors,
wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and
a third layer comprising third transistors each comprising a single crystal silicon channel, said third layer underlying said first transistors,
wherein a plurality of said third transistors form a logic circuit,
wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error, and
wherein said first transistors are junction-less transistors.
9. The 3D semiconductor device according to claim 8 ,
wherein said second layer thickness is less than one micron.
10. The 3D semiconductor device according to claim 8 ,
wherein said first layer comprises a floating body memory cell.
11. The 3D semiconductor device according to claim 8 ,
wherein said first layer comprises independently addressable double-gate transistors.
12. The 3D semiconductor device according to claim 8 ,
wherein said first layer thickness is less than one micron.
13. The 3D semiconductor device according to claim 8 ,
wherein said 3D semiconductor device comprises an electrically modifiable resistive element.
14. The 3D semiconductor device according to claim 8 ,
wherein at least one of said first transistors are directly connected to at least one of said second transistors.
15. A 3D semiconductor device, the device comprising:
a first layer comprising first transistors each comprising a silicon channel;
a second layer comprising second transistors each comprising a silicon channel, said second layer overlaying said first transistors,
wherein at least one of said second transistors is at least partially self-aligned to at least one of said first transistors; and
a third layer comprising third transistors each comprising a single crystal silicon channel, said third structure underlying said first transistors,
wherein a plurality of said third transistors form a logic circuit,
wherein said logic circuit is aligned to said second transistors with less than 200 nm alignment error,
wherein said first layer thickness is less than one micron, and
wherein said second transistors are junction-less transistors.
16. The 3D semiconductor device according to claim 15 ,
wherein said second layer thickness is less than one micron.
17. The 3D semiconductor device according to claim 15 ,
wherein said first layer comprises a floating body memory cell.
18. The 3D semiconductor device according to claim 15 ,
wherein said first layer comprises independently addressable double-gate transistors.
19. The 3D semiconductor device according to claim 15 ,
wherein said 3D semiconductor device comprises an electrically modifiable resistive element.
20. The 3D semiconductor device according to claim 15 ,
wherein at least one of said first transistors are directly connected to at least one of said second transistors.