Granted Patent B2

US 10,811,494 · App. 16/181,051 · Granted Oct 20, 2020

Inventors: Dumitru Gheorge Sdrulla (Bend, OR); Avinash Srikrishnan Kashyap (Portland, OR)

Assignee: Microsemi Corporation

H01L29/0626H01L29/1095H01L29/41741H01L29/66712H01L29/66719H01L29/7802H01L29/1608

Abstract

Claims (31)

1. A power transistor assembly comprising:

a first layer of semiconductor material formed of a first conductivity type material;

a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of said first layer;

a first region formed in said first layer of semiconductor material of a second conductivity type material and aligned with said window, said first region extending from said surface into said first layer a first depth;

one or more source regions formed of first conductivity type material within said first region; and

an extension of said first region extending laterally through said surface of said first layer, said extension of said first region extending from said surface into said first layer a second depth, the second depth being less than the first depth, wherein said extension of said first region comprises a plurality of serial extensions, each of said serial extensions formed separately from each other of said serial extensions.

2. The power transistor assembly of claim 1 , wherein said first layer is an epitaxially formed substrate of silicon carbide (SiC).

3. The power transistor assembly of claim 1 , wherein said hard mask layer comprises a layer of a polysilicon material.

4. The power transistor assembly of claim 3 , wherein said hard mask layer comprises a thin oxide layer.

5. The power transistor assembly of claim 1 , wherein said one or more source regions form a pn junction with the first region.

6. The power transistor assembly of claim 1 , further comprising a drain region formed on a side of said first layer opposite said one or more source regions.

7. A method of mitigating short channel effects in a power transistor assembly, said method comprising:

forming a hard mask layer over a first surface of a substrate formed of a silicon carbide material, the hard mask layer having an outer surface and an inner surface relative to the substrate, and a face extending between the inner surface and the outer surface, a distance between the inner surface and outer surface defining a thickness of the hard mask layer;

opening a window through the hard mask layer to the first surface of the substrate;

implanting impurities in the first surface of the substrate to form a body region approximately aligned with the window;

forming a source region in the body region;

oxidizing the face of the hard mask layer; etching away the oxidized face of the hard mask layer; and

implanting additional impurities into the first surface of the substrate proximate the etched oxidized face forming a lateral extension of the body region extending away from the source region in a direction of the hard mask layer.

8. The method of claim 7 , wherein forming a hard mask layer comprises forming a hard mask layer of a polysilicon material.

9. The method of claim 7 , wherein forming a hard mask layer over a first surface of a substrate formed of a silicon carbide material comprises forming a hard mask layer over the first surface of the substrate formed of a first conductivity type silicon carbide material.

10. The method of claim 9 , wherein implanting impurities in the first surface of the substrate to form a body region comprises implanting impurities in the first surface of the substrate having a second conductivity type silicon carbide material, the second conductivity type silicon carbide material being different than the first conductivity type silicon carbide material.

11. The method of claim 9 , wherein forming a source region in the body region comprises implanting impurities in the first surface of the substrate having the first conductivity type silicon carbide material.

12. The method of claim 7 , wherein forming a hard mask layer over a first surface of a substrate formed of a silicon carbide material comprises forming a relatively thin oxide layer over the first surface of the substrate and forming the hard mask layer over a surface of the relatively thin oxide layer.

13. The method of claim 7 , further comprising forming a drain region on a second surface of the substrate opposite the hard mask layer.

14. A power semiconductor assembly comprising:

a semiconductor substrate formed of an N-type material and having a first impurity concentration;

a P-well formed on a first surface of the semiconductor substrate and having a second impurity concentration, the second impurity concentration greater than the first impurity concentration of the semiconductor substrate;

an N-type source region formed on the first surface of the semiconductor substrate in the P-well and having a third impurity concentration that is greater than the first impurity concentration;

at least one P-type extension region formed in the first surface of the semiconductor substrate and extending laterally away from the N-type source region, wherein the at least one P-type extension region comprises a plurality of serial extensions, each of the serial extensions formed separately from each other of the serial extensions; and

a gate insulating film formed on the first surface of the semiconductor substrate, wherein the N-type source region includes a first N-type source region on one side of the gate insulating film and a second N-type source region on the opposite side of the gate insulating film.

15. The power semiconductor assembly of claim 14 , further comprising a drain region on a second surface of the semiconductor substrate opposite said first surface.

Assignments (16)

Continuity (2)

Cited By (1)

US 12,266,531