IP Library Granted Patent US 10,720,217
Granted Patent B1
US 10,720,217 · App. 16/382,060 · Granted Jul 21, 2020

Memory device and method for varying program state separation based upon frequency of use

Inventors: Hieu Van Tran (San Jose, CA); Steven Lemke (Boulder Creek, CA); Vipin Tiwari (Dublin, CA); Nhan Do (Saratoga, CA); Mark Reiten (Alamo, CA)
Assignee: Silicon Storage Technology, Inc.
G11C16/10G06N3/0454G11C11/54G11C14/00G11C16/0425G11C16/26H01L27/11521
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Quick Facts
Patent No.
US 10,720,217
App. No.
16/382,060
Granted
Jul 21, 2020
Kind
B1
Abstract

A memory device includes a plurality of memory cells and a controller. The controller is configured to program each of the memory cells to one of a plurality of program states, and to read the memory cells using a read operation of applied voltages to the memory cells. During the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.

Claims (84)

1. A memory device, comprising:

a plurality of memory cells;

a controller configured to:

program each of the memory cells to one of a plurality of program states, read the memory cells using a read operation of applied voltages to the memory cells,

wherein during the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells.

2. The memory device of claim 1 , wherein for each of the plurality of program states, the controller is configured to:

determine the frequency of use of the program state in the plurality of memory cells, and

set the separation between the program state and an adjacent one of the program states based upon the determined frequency of use.

3. The memory device of claim 2 , wherein the controller is configured to set the separation for a first of the program states having a first frequency of use and to set the separation for a second of the program states having a second frequency of use that is greater than the first frequency of use, wherein the separation for the second of the program states is greater than the separation for the first of the program states.

4. The memory device of claim 2 , wherein the controller is configured to set the separations for a first group of the program states to a first value, and to set the separations for a second group of the program states to a second value greater than the first value, wherein each of the second group of the program states has a frequency of use greater than that of any of the first group of the program states.

5. The memory device of claim 1 , wherein the plurality of memory cells are non-volatile memory cells.

6. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:

a plurality of memory cells;

a controller configured to:

program each of the memory cells to one of a plurality of program states,

read the memory cells using a read operation of applied voltages to the memory cells,

wherein during the read operation, separations between adjacent ones of the program states vary based on frequencies of use of the program states in the plurality of memory cells;

the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the plurality of program states; and

a first plurality of neurons configured to receive the first plurality of outputs.

7. The neural network device of claim 6 , wherein for each of the plurality of program states, the controller is configured to:

determine the frequency of use of the program state in the plurality of memory cells, and

set the separation between the program state and an adjacent one of the program states based upon the determined frequency of use.

8. The neural network device of claim 7 , wherein the controller is configured to set the separation for a first of the program states having a first frequency of use and to set the separation for a second of the program states having a second frequency of use that is greater than the first frequency of use, wherein the separation for the second of the program states is greater than the separation for the first of the program states.

9. The neural network device of claim 7 , wherein the controller is configured to set the separations for a first group of the program states to a first value, and to set the separations for a second group of the program states to a second value greater than the first value, wherein each of the second group of the program states has a frequency of use greater than that of any of the first group of the program states.

10. The neural network device of claim 6 , further comprising:

a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate therefrom a second plurality of outputs, wherein the second plurality of synapses comprises:

a plurality of second memory cells;

the controller configured to:

program each of the second memory cells to one of a plurality of second program states,

read the second memory cells using a second read operation of second applied voltages to the second memory cells,

wherein during the second read operation, separations between adjacent ones of the second program states vary based on frequencies of use of the second program states in the plurality of second memory cells;

the plurality of second memory cells are configured to generate the second plurality of outputs based upon the second plurality of inputs and the plurality of second program states; and

a second plurality of neurons configured to receive the second plurality of outputs.

11. The neural network device of claim 10 , wherein for each of the plurality of second program states, the controller is configured to:

determine the frequency of use of the second program state in the plurality of second memory cells, and

set the separation between the second program state and an adjacent one of the second program states based upon the determined frequency of use.

12. The neural network device of claim 11 , wherein the controller is configured to set the separation for a first of the second program states having a third frequency of use and to set the separation for a second of the second program states having a fourth frequency of use that is greater than the third frequency of use, wherein the separation for the second of the second program states is greater than the separation for the first of the second program states.

13. The neural network device of claim 11 , wherein the controller is configured to set the separations for a first group of the second program states to a third value, and to set the separations for a second group of the second program states to a fourth value greater than the third value, wherein each of the second group of the second program states has a frequency of use greater than that of any of the first group of the second program states.

14. The neural network device of claim 10 , wherein values of the separations between adjacent ones of the program states are different than values of the separations between adjacent ones of the second program states.

15. The neural network device of claim 10 , wherein a total number of the plurality of program states is different than a total number of the plurality of second program states.

16. The neural network device of claim 10 , wherein the memory cells are volatile and the second memory cells are non-volatile, or the memory cells are non-volatile and the second memory cells are volatile.

17. The neural network device of claim 10 , wherein the plurality of memory cells are non-volatile memory cells and wherein the plurality of second memory cells are non-volatile memory cells.

18. A method of programming memory cells, comprising:

programming each of a plurality of memory cells to one of a plurality of program states;

reading the memory cells using a read operation of applied voltages to the memory cells,

determining a frequency of use for each of the program states in the plurality of memory cells; and

for each of the program states, setting a separation between the program state and an adjacent one of the program states during the read operation based upon the determined frequency of use for the program state.

19. The method of claim 18 , wherein the setting further comprises:

setting the separation for a first of the program states having a first frequency of use; and

setting the separation for a second of the program states having a second frequency of use that is greater than the first frequency of use;

wherein the separation for the second of the program states is greater than the separation for the first of the program states.

20. The method of claim 18 , wherein the setting further comprises:

setting the separations for a first group of the program states to a first value; and

setting the separations for a second group of the program states to a second value greater than the first value;

wherein each of the second group of the program states has a frequency of use greater than that of any of the first group of the program states.

21. A neural network device, comprising:

a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises:

a plurality of first memory cells;

a controller configured to:

program each of the first memory cells to one of a plurality of first program states, and

read the first memory cells using a read operation of applied voltages to the first memory cells,

the plurality of first memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the plurality of first program states; and

a first plurality of neurons configured to receive the first plurality of outputs;

a second plurality of synapses configured to receive a second plurality of inputs from the first plurality of neurons and to generate therefrom a second plurality of outputs, wherein the second plurality of synapses comprises:

a plurality of second memory cells;

the controller configured to:

program each of the second memory cells to one of a plurality of second program states,

read the second memory cells using a second read operation of second applied voltages to the second memory cells,

the plurality of second memory cells are configured to generate the second plurality of outputs based upon the second plurality of inputs and the plurality of second program states; and

a second plurality of neurons configured to receive the second plurality of outputs;

wherein at least one of:

a total number of the plurality of first program states is different than a total number of the plurality of second program states,

a total number of the plurality of first program states is only two and a total number of the plurality of second program states greater than two, or a total number of the plurality of first program states is greater than two and a total number of the plurality of second program states only two,

the first memory cells are volatile and the second memory cells are non-volatile, or the first memory cells are non-volatile and the second memory cells are volatile,

the first memory cells and the second memory cells are non-volatile,

the controller is configured perform the first read operation above threshold and the second read operation below threshold, or perform the first read operation below threshold and the second read operation above threshold, and

the controller is configured perform the first read operation and the second read operation above threshold, or perform the first read operation and the second read operation below threshold.

22. The neural network device of claim 21 , wherein a total number of the plurality of first program states is different than a total number of the plurality of second program states.

23. The neural network device of claim 21 , wherein a total number of the plurality of first program states is only two and a total number of the plurality of second program states greater than two, or a total number of the plurality of first program states is greater than two and a total number of the plurality of second program states only two.

24. The neural network device of claim 21 , wherein the first memory cells are volatile and the second memory cells are non-volatile, or the first memory cells are non-volatile and the second memory cells are volatile.

25. The neural network device of claim 21 , wherein the first memory cells and the second memory cells are non-volatile.

26. The neural network device of claim 21 , wherein the controller is configured perform the first read operation above threshold and the second read operation below threshold, or perform the first read operation below threshold and the second read operation above threshold.

27. The neural network device of claim 21 , wherein the controller is configured perform the first read operation and the second read operation above threshold, or perform the first read operation and the second read operation below threshold.

Assignments (16)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2019
From: TRAN, HIEU VAN; LEMKE, STEVEN; TIWARI, VIPIN; DO, NHAN; REITEN, MARK
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 048944/0386 →
Continuity (1)
Provisional Application 62798417 · Jan 29, 2019
Cited By (4)
US 12,237,011 US 12,249,368 US 12,283,314 US 12,354,651