Display device and electronic device including the same
View Patent ↗It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.
1. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a first gate line, a second gate line, and a third gate line,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first gate line,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second gate line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the gate electrode of the first transistor,
wherein a gate electrode of the third transistor is electrically connected to the third gate line,
wherein, in the first transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is larger than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the second transistor, an area where a gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other, and
wherein, in the third transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other.
2. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a first gate line, a second gate line, a third gate line, a clock signal line, and a power supply line,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first gate line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to the clock signal line,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second gate line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to the power supply line,
wherein a gate electrode of the third transistor is electrically connected to the third gate line,
wherein, in the first transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is larger than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the second transistor, an area where a gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other, and
wherein, in the third transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other.
3. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a first gate line, a second gate line, a third gate line, a first clock signal line, a second clock signal line, and a power supply line,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first gate line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to the first clock signal line through a conductive layer,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second gate line,
wherein a gate electrode of the second transistor is electrically connected to the second clock signal line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to the power supply line,
wherein a gate electrode of the third transistor is electrically connected to the third gate line,
wherein, in the first transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is larger than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the second transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the third transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other, and
wherein the conductive layer comprises a region overlapping with an opening portion of the second clock signal line.
4. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a first gate line, and a second gate line,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first gate line,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second gate line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the first gate line,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the second gate line,
wherein a gate electrode of the fourth transistor is electrically connected to the second gate line,
wherein, in the first transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is larger than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the second transistor, an area where a gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other, and
wherein, in the third transistor, an area where a gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other.
5. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a first gate line, a second gate line, a first clock signal line, a second clock signal line, and a power supply line,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first gate line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to the first clock signal line,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second gate line,
wherein a gate electrode of the second transistor is electrically connected to the second clock signal line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the first gate line,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to the power supply line,
wherein a gate electrode of the third transistor is electrically connected to the second clock signal line,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the second gate line,
wherein a gate electrode of the fourth transistor is electrically connected to the second gate line,
wherein, in the first transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is larger than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the second transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other, and
wherein, in the third transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other.
6. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a first gate line, a second gate line, a first clock signal line, a second clock signal line, and a power supply line,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first gate line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to the first clock signal line through a conductive layer,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to the second gate line,
wherein a gate electrode of the second transistor is electrically connected to the second clock signal line,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the first gate line,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to the power supply line,
wherein a gate electrode of the third transistor is electrically connected to the second clock signal line,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the second gate line,
wherein a gate electrode of the fourth transistor is electrically connected to the second gate line,
wherein, in the first transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is larger than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the second transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the third transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other, and
wherein the conductive layer comprises a region overlapping with an opening portion of the second clock signal line.
7. A semiconductor device comprising:
a first stage and a second stage,
wherein each of the first stage and the second stage comprises a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor,
wherein the one of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor,
wherein a gate electrode of the third transistor is electrically connected to a gate electrode of the fourth transistor,
wherein the one of the source electrode and the drain electrode of the first transistor of the first stage is electrically connected to the second stage,
wherein the other of the source electrode and the drain electrode of the second transistor of the first stage is electrically connected to a wiring,
wherein the other of the source electrode and the drain electrode of the third transistor of the first stage is electrically connected to the wiring,
wherein the other of the source electrode and the drain electrode of the fourth transistor of the first stage is electrically connected to the wiring,
wherein the other of the source electrode and the drain electrode of the second transistor of the second stage is electrically connected to the wiring,
wherein the other of the source electrode and the drain electrode of the third transistor of the second stage is electrically connected to the wiring,
wherein the other of the source electrode and the drain electrode of the fourth transistor of the second stage is electrically connected to the wiring,
wherein, in the first transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is larger than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the second transistor, an area where a gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the third transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the fourth transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other.
8. A semiconductor device comprising:
a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor,
wherein the one of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor,
wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a gate electrode of the first transistor,
wherein a gate electrode of the third transistor is electrically connected to a gate electrode of the fourth transistor,
wherein the one of the source electrode and the drain electrode of the first transistor is electrically connected to a wiring which outputs a signal,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a power supply line,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to the power supply line,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the power supply line,
wherein, in the first transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is larger than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the second transistor, an area where a gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the third transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other,
wherein, in the fourth transistor, an area where the gate electrode and the one of the source electrode and the drain electrode overlap with each other is smaller than an area where the gate electrode and the other of the source electrode and the drain electrode overlap with each other.