Multi-chip module (MCM) with chip-to-chip connection redundancy and method
Disclosed is a multi-chip module (MCM) with redundant chip-to-chip communication connection(s) to minimize the need to discard a chip-mounting layer due to defective signal traces. The MCM includes at least first and second chips mounted on the chip-mounting layer. The chip-mounting layer includes signal traces that are electrically connected between first and second links on the first and second chips, respectively, to form communication connections including at least one redundant communication connection. Instead of being directly connected to the chip-to-chip communication connections, first and second interfaces on the first and second chips are connected via first and second multiplexors, respectively, to selected ones of multiple chip-to-chip communication connections. By employing the multiplexors and the redundant chip-to-chip communication connection(s), chip-to-chip communication connection(s) with defective signal trace(s) can be bypassed. Specifically, during MCM assembly, the multiplexors are programmed to avoid using chip-to-chip communication connections with defective signal traces.
1. A multi-chip module comprising:
a chip-mounting layer comprising signal traces; and
at least a first chip and a second chip mounted on a surface of the chip-mounting layer,
wherein the first chip comprises first links and the second chip comprises second links,
wherein each signal trace is electrically connected to a first link on the first chip and to a second link on the second chip to form a chip-to-chip communication connection,
wherein the first chip further comprises first interfaces and first multiplexors with each first multiplexor being connected between one first interface and multiple first links and the second chip further comprises second interfaces and second multiplexors with each second multiplexor being connected between one second interface and multiple second links, and
wherein each pair of first and second interfaces is selectively connectable by a corresponding pair of first and second multiplexors to one of multiple chip-to-chip communication connections.
2. The multi-chip module of claim 1 , further comprising at least one redundant chip-to-chip communication connection, wherein the first multiplexors, the second multiplexors, and the at least one redundant chip-to-chip communication connection enable at least one chip-to-chip communication connection with a defective signal trace to be bypassed.
3. The multi-chip module of claim 1 , further comprising multiple chip-to-chip communication sections, each section comprising:
a first number of pairs of first and second interfaces and of pairs of first and second multiplexors; and
a second number of pairs of first and second links, of signal traces and of chip-to-chip communication connections, wherein the second number is greater than the first number by one so that the section comprises one redundant chip-to chip communication connection, and
wherein the first multiplexors, the second multiplexors and the one redundant chip-to chip communication connection in the section enable one chip-to-chip communication connection within the section and having a defective signal trace to be bypassed.
4. The multi-chip module of claim 1 , wherein the chip-mounting layer further comprises a coded region identifying any detected defective signal traces within the chip-mounting layer and wherein the coded region is readable during module assembly to program the first multiplexors and the second multiplexors.
5. The multi-chip module of claim 4 , wherein the coded region comprises a bar code region.
6. The multi-chip module of claim 4 , wherein the coded region comprises a one-time programmable non-volatile memory comprising any of fuses and anti-fuses.
7. The multi-chip module of claim 4 , wherein the coded region comprises a chiplet.
8. The multi-chip module of claim 1 , wherein the chip-mounting layer comprises any of a substrate and an interposer mounted on a substrate.
9. The multi-chip module of claim 1 , wherein the first interfaces and the second interfaces comprise serializer/deserializer function blocks and the first links and the second links comprise input/output ports.
10. A multi-chip module comprising:
a substrate comprising signal traces, wherein a size of the substrate is at least 5625 mm 2 ; and
multiple chips mounted on the substrate and comprising at least a first chip and a second chip,
wherein a size of at least one of the chips is above 400 mm 2 ,
wherein the first chip comprises first links and the second chip comprises second links,
wherein each signal trace is electrically connected to a first link on the first chip and to a second link on the second chip to form a chip-to-chip communication connection,
wherein the first chip further comprises first interfaces and first multiplexors with each first multiplexor being connected between one first interface and multiple first links and the second chip further comprises second interfaces and second multiplexors with each second multiplexor being connected between one second interface and multiple second links, and
wherein each pair of first and second interfaces is selectively connectable by a pair of corresponding first and second multiplexors to one of multiple chip-to-chip communication connections.
11. The multi-chip module of claim 10 , further comprising at least one redundant chip-to-chip communication connection, wherein the first multiplexors, the second multiplexors, and the at least one redundant chip-to-chip communication connection enable at least one chip-to-chip communication connection with a defective signal trace to be bypassed.
12. The multi-chip module of claim 10 , further comprising multiple chip-to-chip communication sections, each section comprising:
a first number of pairs of first and second interfaces and of pairs of first and second multiplexors; and
a second number of pairs of first and second links, of signal traces and of chip-to-chip communication connections, wherein the second number is greater than the first number by one so that the section comprises one redundant chip-to chip communication connection, and
wherein the first multiplexors, the second multiplexors and the one redundant chip-to chip communication connection in the section enable one chip-to-chip communication connection within the section and having a defective signal trace to be bypassed.
13. The multi-chip module of claim 10 , wherein the substrate further comprises a coded region identifying any previously detected defective signal traces within a chip-mounting layer and wherein the coded region is readable during module assembly to program the first multiplexors and the second multiplexors.
14. The multi-chip module of claim 10 , wherein the first interfaces and the second interfaces comprise serializer/deserializer function blocks and the first links and the second links comprise input/output ports.
15. A method comprising:
mounting a first chip and a second chip on a surface of a chip-mounting layer in designated chip-mounting areas,
wherein the chip-mounting layer comprises signal traces between the designated chip-mounting areas,
wherein the first chip comprises first interfaces, first links, and first multiplexors with each first multiplexor being connected between one first interface and multiple first links,
wherein the second chip comprises second interfaces, second links, and second multiplexors with each second multiplexor being connected between one second interface and multiple second links, and
wherein, during the mounting, each signal trace is electrically connected to a first link on the first chip and to a second link on the second chip to form chip-to-chip communication connections; and
using each pair of first and second multiplexors to connect a corresponding pair of first and second interfaces to a selected one of at least two of the chip-to-chip communication connections.
16. The method of claim 15 ,
wherein at least one of the chip-to-chip communication connections is a redundant chip-to-chip communication connection, and
wherein the method further comprises:
before the mounting, reading defect information identifying defective signal traces within the chip-mounting layer; and
given the redundant chip-to-chip communication connection and based on the defect information, using the first multiplexors and the second multiplexors to bypass at least one chip-to-chip communication connection with a defective signal trace.
17. The method of claim 16 , further comprising:
during manufacturing of the chip-mounting layer, performing optical inspections; and
following manufacturing of the chip-mounting layer, performing electrical tests, wherein results of the optical inspections and the electrical tests are used to identify the defective signal traces.
18. The method of claim 16 ,
wherein the reading of the defect information comprises automatically reading a coded region that is on the chip-mounting layer and that identifies any previously detected defective signal traces within the chip-mounting layer, and
wherein the coded region comprises any of a bar code, a one-time programmable non-volatile memory comprising any of fuses and anti-fuse, and a chiplet in the coded region.
19. The method of claim 15 , wherein the chip-mounting layer comprises any of a substrate and an interposer mounted on a substrate.
20. The method of claim 15 , wherein the first interfaces and the second interfaces comprise serializer/deserializer function blocks and the first links and the second links comprise input/output ports.