Wafer-level bonding of obstructive elements
A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.
1. A bonded structure comprising:
a semiconductor element comprising active circuitry;
an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry; and
an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.
2. The bonded structure of claim 1 , wherein the obstructive material is positioned at a distance less than 10 microns from the bond interface.
3. The bonded structure of claim 1 , wherein the obstructive material comprises a destructive material having a hardness in a range of 13 GPa to 150 GPa.
4. The bonded structure of claim 1 , wherein the artifact structure includes markings on the obstructive material indicative of a patterning process performed prior to bonding.
5. The bonded structure of claim 1 , wherein the artifact structure comprises a first sidewall of the semiconductor element being flush with a second sidewall of the obstructive element.
6. The bonded structure of claim 1 , further comprising a first bonding layer on the semiconductor element and a second bonding layer on the obstructive element, the first and second bonding layers directly bonded to one another without an adhesive.
7. The bonded structure of claim 6 , wherein the artifact structure comprises a trench formed through a back side of the obstructive element through the obstructive material to expose a bond pad on the semiconductor element.
8. The bonded structure of claim 7 , wherein the trench extends through the second bonding layer to the bond interface.
9. The bonded structure of claim 7 , further comprising a bond wire electrically connected to the bond pad in the trench.
10. The bonded structure of claim 7 , further comprising a conductive trace extending from the bond pad in the trench to the back side of the obstructive element.
11. The bonded structure of claim 7 , further comprising a dielectric liner disposed along a vertical sidewall of the trench, the dielectric liner extending towards the back side of the obstructive element.
12. The bonded structure of claim 6 , wherein the artifact structure comprises a lateral side surface of the obstructive element including saw markings indicative of a saw cut.
13. The bonded structure of claim 12 , wherein the artifact structure comprises the lateral side surface of the obstructive element also including an etch pattern indicative of an etching process.
14. The bonded structure of claim 6 , wherein the artifact structure comprises a lateral side surface of the obstructive element including an etch pattern indicative of an etching process.
15. The bonded structure of claim 14 , wherein the etch pattern is indicative of an etch pathway extending towards a back side of the obstructive element that faces away from the bond interface, the lateral side surface of the obstructive element also comprising a second etch pattern indicative of a second etch pathway extending away from the back side of the obstructive element.
16. The bonded structure of claim 6 , wherein the semiconductor element comprises an active semiconductor region including the active circuitry and a bulk semiconductor region, the first bonding layer disposed on the bulk semiconductor region such that the bulk semiconductor region is between the active semiconductor region and the first bonding layer.
17. The bonded structure of claim 6 , wherein the semiconductor element comprises an active semiconductor region including the active circuitry, the first bonding layer disposed on the active semiconductor region.
18. A method for forming a bonded structure, the method comprising:
directly bonding a semiconductor element having active circuitry to a wafer without an adhesive, the wafer comprising an obstructive material configured to obstruct external access to the active circuitry; and
after the directly bonding, singulating the wafer to form a plurality of singulated bonded structures.
19. The method of claim 18 , wherein the semiconductor element comprises a second wafer that includes the active circuitry, the method comprising singulating the second wafer after the directly bonding.
20. The method of claim 18 , further comprising patterning the obstructive material before the directly bonding.
21. The method of claim 20 , further comprising partially sawing or partially etching through the wafer before the directly bonding.
22. The method of claim 20 , further comprising applying the obstructive material over a patterned additive material, applying a dielectric layer over the obstructive material, and removing portions of the obstructive material and the dielectric layer to form openings in the obstructive material.
23. The method of claim 18 , further comprising, after the directly bonding, forming a trench through a back side of the wafer through the obstructive material to a bond pad on the semiconductor element.
24. The method of claim 18 , further comprising forming the semiconductor element before the directly bonding, the semiconductor element comprising a bulk semiconductor region and an active semiconductor region over the bulk semiconductor region, wherein forming the semiconductor element comprises bonding a handle element to the active semiconductor region.
25. The method of claim 24 , further comprising removing a portion of the bulk semiconductor region after bonding the handle element to form an exposed back surface of the bulk semiconductor region, providing a first bonding layer on the exposed back surface of the bulk semiconductor region, and removing the handle element after the directly bonding.
26. The method of claim 18 , further comprising forming the semiconductor element before the directly bonding, the semiconductor element comprising a bulk semiconductor region and an active semiconductor region over the bulk semiconductor region, wherein forming the semiconductor element comprises providing a first bonding layer on the active semiconductor region.
27. The method of claim 26 , wherein the active semiconductor region comprises an active silicon layer over a buried oxide (BOX) layer.
28. The method of claim 26 , further comprising providing a second bonding layer on the obstructive material, wherein the directly bonding comprises directly bonding the first and second bonding layers without an adhesive.